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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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c91735b23b2bf60d2f3067530cff856491e149b3
OpenRAM/technology/scn3me_subm/gds_lib
T
History
Matt Guthaus 763f1e8dee Finish renaming replica bitcell and bitline pin names.
2018-09-04 14:03:15 -07:00
..
cell_6t.gds
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
dff.gds
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
ms_flop.gds
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
replica_cell_6t.gds
Finish renaming replica bitcell and bitline pin names.
2018-09-04 14:03:15 -07:00
sense_amp.gds
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
tri_gate.gds
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
write_driver.gds
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
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