mirror of https://github.com/VLSIDA/OpenRAM.git
57 lines
1.3 KiB
Python
57 lines
1.3 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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"""
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This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools.
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"""
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import debug
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# Only print the warning once.
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drc_warned = False
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lvs_warned = False
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pex_warned = False
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def run_drc(cell_name, gds_name, extract=False, final_verification=False):
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global drc_warned
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if not drc_warned:
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debug.error("DRC unable to run.", -1)
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drc_warned=True
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# Since we warned, return a failing test.
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return 1
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def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
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global lvs_warned
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if not lvs_warned:
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debug.error("LVS unable to run.", -1)
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lvs_warned=True
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# Since we warned, return a failing test.
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return 1
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def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
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global pex_warned
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if not pex_warned:
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debug.error("PEX unable to run.", -1)
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pex_warned=True
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# Since we warned, return a failing test.
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return 1
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def print_drc_stats():
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pass
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def print_lvs_stats():
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pass
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def print_pex_stats():
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pass
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