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c6503dd77199ad8114b4bf5a5c925ff6342dcd54
OpenRAM/compiler/tests
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Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so 
that they don't use old parameters after a failure.
2018-07-10 16:39:32 -07:00
..
golden
Initial merge of incomplete multi-port clean with new supply routing.
2018-05-11 08:18:04 -07:00
00_code_format_check_test.py
Change permissions of tests to be executable so you don't have to type python each time.
2018-06-29 11:36:30 -07:00
01_library_drc_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
02_library_lvs_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_contact_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_path_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_1finger_nmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_1finger_pmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_3finger_nmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_3finger_pmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_4finger_nmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_ptx_4finger_pmos_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
03_wire_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pbitcell_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_1x_beta_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_1x_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_2x_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinv_10x_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pinvbuf_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pnand2_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pnand3_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_pnor2_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_precharge_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
04_single_level_column_mux_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
05_bitcell_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
05_pbitcell_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
06_hierarchical_decoder_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
06_hierarchical_predecode2x4_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
06_hierarchical_predecode3x8_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
07_single_level_column_mux_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
08_precharge_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
08_wordline_driver_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
09_sense_amp_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
10_write_driver_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_buf_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_buf_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_inv_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_dff_inv_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
11_ms_flop_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
12_tri_gate_array_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
13_delay_chain_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
14_replica_bitline_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
16_control_logic_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
19_bank_select_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
19_multi_bank_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
19_single_bank_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
20_sram_1bank_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
20_sram_2bank_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
20_sram_4bank_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
21_hspice_delay_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
21_hspice_setuphold_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
21_ngspice_delay_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
21_ngspice_setuphold_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
22_pex_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
22_sram_func_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
23_lib_sram_model_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
23_lib_sram_prune_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
23_lib_sram_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
24_lef_sram_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
25_verilog_sram_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
30_openram_test.py
Add getpass include to unit test 30
2018-07-09 15:53:37 -07:00
config_20_freepdk45.py
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
config_20_scn3me_subm.py
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
README
RELEASE 1.0
2016-11-08 09:57:35 -08:00
regress.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
testutils.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00

README 

Note that the tests turn off DRC/LVS when they perform their own check
for performance improvement. However, it must be turned back on before
the test runs an assert.
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