mirror of https://github.com/VLSIDA/OpenRAM.git
65 lines
2.2 KiB
Python
65 lines
2.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from tech import GDS, layer, spice
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from tech import cell_properties as props
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import utils
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class dff(design.design):
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"""
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Memory address flip-flop
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"""
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if not props.dff.use_custom_ports:
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pin_names = ["D", "Q", "clk", "vdd", "gnd"]
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type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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clk_pin = "clk"
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else:
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pin_names = props.dff.custom_port_list
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type_list = props.dff.custom_type_list
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clk_pin = props.dff.clk_pin
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cell_size_layer = "boundary"
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def __init__(self, name="dff"):
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super().__init__(name)
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(width, height) = utils.get_libcell_size(self.cell_name,
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GDS["unit"],
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layer[self.cell_size_layer])
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pin_map = utils.get_libcell_pins(self.pin_names,
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self.cell_name,
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GDS["unit"])
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self.width = width
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self.height = height
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self.pin_map = pin_map
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self.add_pin_types(self.type_list)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["dff_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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c_para = spice["dff_out_cap"]#ff
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transition_prob = 0.5
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return transition_prob*(c_load + c_para)
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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