mirror of https://github.com/VLSIDA/OpenRAM.git
82 lines
3.3 KiB
Python
82 lines
3.3 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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import utils
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from tech import GDS, layer, drc, parameter, cell_properties
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from tech import cell_properties as props
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from globals import OPTS
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class replica_bitcell(design.design):
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"""
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A single bit cell (6T, 8T, etc.)
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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if props.compare_ports(props.bitcell.split_wl):
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pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
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else:
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pin_names = [props.bitcell.cell_6t.pin.bl,
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props.bitcell.cell_6t.pin.br,
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props.bitcell.cell_6t.pin.wl,
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props.bitcell.cell_6t.pin.vdd,
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props.bitcell.cell_6t.pin.gnd]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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def __init__(self, version, name=""):
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# Ignore the name argument
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if version == "opt1":
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self.name = "s8sram_cell_opt1"
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self.border_structure = "s8sram_cell"
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elif version == "opt1a":
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self.name = "s8sram_cell_opt1a"
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self.border_structure = "s8sram_cell"
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self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
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design.design.__init__(self, "replica_cell_6t")
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debug.info(2, "Create replica bitcell object")
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self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
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self.add_pin_types(self.type_list)
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"])
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def get_stage_effort(self, load):
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parasitic_delay = 1
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size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
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cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
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read_port_load = 0.5 #min size NMOS gate load
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return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
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def input_load(self):
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"""Return the relative capacitance of the access transistor gates"""
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# FIXME: This applies to bitline capacitances as well.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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def analytical_power(self, corner, load):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
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total_power = self.return_power(dynamic, leakage)
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return total_power
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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