mirror of https://github.com/VLSIDA/OpenRAM.git
53 lines
1.9 KiB
Python
53 lines
1.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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import utils
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from tech import GDS,layer,drc,parameter,cell_properties
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class s8_dummy_bitcell(bitcell_base.bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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if props.compare_ports(props.bitcell.split_wl):
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pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
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else:
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pin_names = [props.bitcell.cell_s8_6t.pin.bl,
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props.bitcell.cell_s8_6t.pin.br,
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props.bitcell.cell_s8_6t.pin.wl,
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"vpwr",
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"vgnd"]
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def __init__(self, version, name=""):
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# Ignore the name argument
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if version == "opt1":
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self.name = "s8sram_cell_opt1"
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self.border_structure = "s8sram_cell"
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elif version == "opt1a":
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self.name = "s8sram_cell_opt1a"
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self.border_structure = "s8sram_cell"
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bitcell_base.bitcell_base.__init__(self, self.name)
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debug.info(2, "Create dummy bitcell")
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"],
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"s8sram_cell\x00")
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self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
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