mirror of https://github.com/VLSIDA/OpenRAM.git
35 lines
1.2 KiB
Python
35 lines
1.2 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import utils
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from tech import layer, GDS
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class s8_corner(design.design):
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def __init__(self, location, name=""):
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super().__init__(name)
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if location == "ul":
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self.name = "s8sram16x16_corner"
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elif location == "ur":
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self.name = "s8sram16x16_cornerb"
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elif location == "ll":
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self.name = "s8sram16x16_cornera"
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elif location == "lr":
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self.name = "s8sram16x16_cornera"
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else:
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debug.error("Invalid s8_corner location", -1)
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design.design.__init__(self, name=self.name)
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"])
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# pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
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