mirror of https://github.com/VLSIDA/OpenRAM.git
104 lines
3.6 KiB
Python
104 lines
3.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import utils
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from tech import GDS, layer
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from tech import cell_properties as props
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import bitcell_base
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class s8_bitcell(bitcell_base.bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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# If we have a split WL bitcell, if not be backwards
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# compatible in the tech file
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if props.compare_ports(props.bitcell.split_wl):
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pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
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else:
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pin_names = [props.bitcell.cell_s8_6t.pin.bl,
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props.bitcell.cell_s8_6t.pin.br,
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props.bitcell.cell_s8_6t.pin.wl,
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"vpwr",
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"vgnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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def __init__(self, version, name=""):
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# Ignore the name argument
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if version == "opt1":
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self.name = "s8sram_cell_opt1"
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elif version == "opt1a":
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self.name = "s8sram_cell_opt1a"
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bitcell_base.bitcell_base.__init__(self, self.name)
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debug.info(2, "Create bitcell")
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self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
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self.add_pin_types(self.type_list)
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self.nets_match = self.do_nets_exist(self.storage_nets)
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"])
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def get_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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if props.compare_ports(props.bitcell.split_wl):
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row_pins = ["wl0", "wl1"]
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else:
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row_pins = [props.bitcell.cell_s8_6t.pin.wl]
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return row_pins
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def get_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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pin = props.bitcell.cell_s8_6t.pin
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column_pins = [pin.bl, pin.br]
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return column_pins
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def get_all_bl_names(self):
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""" Creates a list of all bl pins names """
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return [props.bitcell.cell_s8_6t.pin.bl]
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def get_all_br_names(self):
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""" Creates a list of all br pins names """
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return [props.bitcell.cell_s8_6t.pin.br]
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def get_bl_name(self, port=0):
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"""Get bl name"""
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debug.check(port == 0, "One port for bitcell only.")
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return props.bitcell.cell_s8_6t.pin.bl
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def get_br_name(self, port=0):
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"""Get bl name"""
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debug.check(port == 0, "One port for bitcell only.")
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return props.bitcell.cell_s8_6t.pin.br
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def get_wl_name(self, port=0):
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"""Get wl name"""
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if props.compare_ports(props.bitcell.split_wl):
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return "wl{}".format(port)
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else:
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debug.check(port == 0, "One port for bitcell only.")
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return props.bitcell.cell_s8_6t.pin.wl
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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