mirror of https://github.com/VLSIDA/OpenRAM.git
45 lines
1.6 KiB
Python
45 lines
1.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import utils
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from tech import GDS, layer
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from tech import cell_properties as props
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import bitcell_base
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class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
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"""
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pin_names = [props.bitcell.cell_1rw1r.pin.wl0,
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props.bitcell.cell_1rw1r.pin.wl1,
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props.bitcell.cell_1rw1r.pin.gnd]
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type_list = ["INPUT", "INPUT", "GROUND"]
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(width, height) = utils.get_libcell_size("row_cap_cell_1rw_1r",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names,
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"row_cap_cell_1rw_1r",
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GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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bitcell_base.bitcell_base.__init__(self, "row_cap_cell_1rw_1r")
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debug.info(2, "Create row_cap bitcell 1rw+1r object")
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self.width = row_cap_bitcell_1rw_1r.width
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self.height = row_cap_bitcell_1rw_1r.height
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self.pin_map = row_cap_bitcell_1rw_1r.pin_map
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self.add_pin_types(self.type_list)
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self.no_instances = True
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