mirror of https://github.com/VLSIDA/OpenRAM.git
118 lines
1.9 KiB
Plaintext
118 lines
1.9 KiB
Plaintext
magic
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tech scmos
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timestamp 1536091415
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<< nwell >>
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rect -8 29 42 51
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<< pwell >>
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rect -8 -8 42 29
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<< ntransistor >>
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rect 7 10 9 18
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rect 29 10 31 18
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rect 10 3 14 5
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rect 24 3 28 5
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<< ptransistor >>
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rect 7 37 11 40
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rect 27 37 31 40
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<< ndiffusion >>
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rect -2 16 7 18
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rect 2 12 7 16
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rect -2 10 7 12
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rect 9 14 10 18
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rect 9 10 14 14
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rect 28 14 29 18
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rect 24 10 29 14
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rect 31 16 36 18
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rect 31 12 32 16
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rect 31 10 36 12
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rect 10 5 14 10
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rect 24 5 28 10
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rect 10 2 14 3
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rect 24 2 28 3
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<< pdiffusion >>
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rect 2 37 7 40
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rect 11 37 12 40
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rect 26 37 27 40
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rect 31 37 32 40
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<< ndcontact >>
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rect -2 12 2 16
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rect 10 14 14 18
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rect 24 14 28 18
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rect 32 12 36 16
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rect 10 -2 14 2
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rect 24 -2 28 2
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<< pdcontact >>
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rect -2 36 2 40
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rect 12 36 16 40
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rect 22 36 26 40
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rect 32 36 36 40
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<< psubstratepcontact >>
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rect -2 22 2 26
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rect 32 22 36 26
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<< nsubstratencontact >>
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rect 32 44 36 48
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<< polysilicon >>
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rect 7 40 11 42
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rect 27 40 31 42
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rect 7 35 11 37
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rect 7 21 9 35
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rect 27 34 31 37
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rect 15 33 31 34
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rect 19 32 31 33
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rect 7 20 21 21
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rect 7 19 24 20
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rect 7 18 9 19
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rect 29 18 31 32
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rect 7 8 9 10
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rect 17 5 21 6
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rect 29 8 31 10
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rect -2 3 10 5
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rect 14 3 24 5
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rect 28 3 36 5
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<< polycontact >>
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rect 15 29 19 33
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rect 21 20 25 24
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rect 17 6 21 10
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<< metal1 >>
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rect -2 44 15 48
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rect 19 44 32 48
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rect -2 40 2 44
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rect 32 40 36 44
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rect 11 36 12 40
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rect 26 36 27 40
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rect -2 26 2 29
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rect -2 16 2 22
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rect 11 18 15 36
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rect 23 24 27 36
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rect 25 20 27 24
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rect 14 14 15 18
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rect 23 18 27 20
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rect 32 26 36 29
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rect 23 14 24 18
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rect 32 16 36 22
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rect -2 6 17 9
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rect 21 6 36 9
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rect -2 5 36 6
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<< m2contact >>
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rect 15 44 19 48
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rect -2 29 2 33
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rect 32 29 36 33
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rect 6 -2 10 2
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rect 20 -2 24 2
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<< metal2 >>
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rect -2 33 2 48
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rect -2 -2 2 29
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rect 6 2 10 48
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rect 24 -2 28 48
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rect 32 33 36 48
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rect 32 -2 36 29
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<< bb >>
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rect 0 0 34 46
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<< labels >>
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rlabel metal2 0 0 0 0 1 gnd
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rlabel metal2 34 0 34 0 1 gnd
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rlabel m2contact 17 46 17 46 5 vdd
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rlabel metal2 8 43 8 43 1 bl
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rlabel metal2 26 43 26 43 1 br
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rlabel metal1 4 7 4 7 1 wl
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<< end >>
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