mirror of https://github.com/VLSIDA/OpenRAM.git
11 lines
314 B
Plaintext
11 lines
314 B
Plaintext
digraph G {
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module [shape=record, label="module\n(e.g., bit-cell array)"];
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design [shape=record, label="design\nDRC_LVS()"];
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hierarchy_layout [shape=record, label="layout\n"];
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hierarchy_spice [shape=record, label="spice\n"];
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module -> design
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design -> hierarchy_layout;
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design -> hierarchy_spice;
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}
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