mirror of https://github.com/VLSIDA/OpenRAM.git
236 lines
8.9 KiB
Python
236 lines
8.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from globals import OPTS
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from sram_factory import factory
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from vector import vector
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import debug
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from numpy import cumsum
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class global_bitcell_array(design.design):
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"""
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Creates a global bitcell array.
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Rows is an integer number for all local arrays.
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Cols is a list of the array widths.
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add_left_rbl and add_right_
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"""
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def __init__(self, rows, cols, name=""):
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# The total of all columns will be the number of columns
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super().__init__(name=name)
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self.cols = cols
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self.num_cols = sum(cols)
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self.col_offsets = [0] + list(cumsum(self.cols)[:-1])
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self.rows = rows
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debug.check(len(self.all_ports)<=2, "Only support dual port or less in global bitcell array.")
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self.rbl = [1, 1 if len(self.all_ports)>1 else 0]
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self.left_rbl = self.rbl[0]
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self.right_rbl = self.rbl[1]
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place()
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self.route()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.local_mods = []
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if self.cols == 1:
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la = factory.create(module_type="local_bitcell_array", rows=self.rows, cols=self.cols[0], rbl=self.rbl, add_rbl=[self.left_rbl, self.right_rbl])
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self.add_mod(la)
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self.local_mods.append(la)
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return
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for i, cols in enumerate(self.cols):
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# Always add the left RBLs to the first subarray and the right RBLs to the last subarray
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if i == 0:
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la = factory.create(module_type="local_bitcell_array", rows=self.rows, cols=cols, rbl=self.rbl, add_rbl=[self.left_rbl, 0])
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elif i == len(self.cols) - 1:
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la = factory.create(module_type="local_bitcell_array", rows=self.rows, cols=cols, rbl=self.rbl, add_rbl=[0, self.right_rbl])
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else:
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la = factory.create(module_type="local_bitcell_array", rows=self.rows, cols=cols, rbl=self.rbl, add_rbl=[0, 0])
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self.add_mod(la)
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self.local_mods.append(la)
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def add_pins(self):
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self.add_bitline_pins()
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self.add_wordline_pins()
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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self.bitline_names = []
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for port in self.all_ports:
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self.bitline_names.append("rbl_bl_{0}_{1}".format(port, 0))
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self.bitline_names.append("rbl_br_{0}_{1}".format(port, 0))
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for col in range(self.num_cols):
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for port in self.all_ports:
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self.bitline_names.append("bl_{0}_{1}".format(port, col))
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self.bitline_names.append("br_{0}_{1}".format(port, col))
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if len(self.all_ports) > 1:
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for port in self.all_ports:
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self.bitline_names.append("rbl_bl_{0}_{1}".format(port, 1))
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self.bitline_names.append("rbl_br_{0}_{1}".format(port, 1))
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self.add_pin_list(self.bitline_names, "INOUT")
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def add_wordline_pins(self):
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self.wordline_names = []
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self.wordline_names.append("rbl_wl_0_0")
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# Regular WLs
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for row in range(self.rows):
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for port in self.all_ports:
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self.wordline_names.append("wl_{0}_{1}".format(port, row))
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if len(self.all_ports) > 1:
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self.wordline_names.append("rbl_wl_1_1")
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self.add_pin_list(self.wordline_names, "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.local_insts = []
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for col, mod in zip(self.col_offsets, self.local_mods):
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name = "la_{0}".format(col)
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self.local_insts.append(self.add_inst(name=name,
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mod=mod))
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temp = []
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if col == 0:
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temp.append("rbl_bl_0_0")
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temp.append("rbl_br_0_0")
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if len(self.all_ports) > 1:
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temp.append("rbl_bl_1_0")
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temp.append("rbl_br_1_0")
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port_inouts = [x for x in mod.get_inouts() if x.startswith("bl") or x.startswith("br")]
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for pin_name in port_inouts:
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# Offset of the last underscore that defines the bit number
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bit_index = pin_name.rindex('_')
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# col is the bit offset of the local array,
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# while col_value is the offset within this array
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col_value = int(pin_name[bit_index + 1:])
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# Name of signal without the bit
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base_name = pin_name[:bit_index]
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# Strip the bit and add the new one
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new_name = "{0}_{1}".format(base_name, col + col_value)
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temp.append(new_name)
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if len(self.all_ports) > 1 and mod == self.local_mods[-1]:
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temp.append("rbl_bl_0_1")
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temp.append("rbl_br_0_1")
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temp.append("rbl_bl_1_1")
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temp.append("rbl_br_1_1")
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for port in self.all_ports:
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port_inputs = [x for x in mod.get_inputs() if "wl_{}".format(port) in x]
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temp.extend(port_inputs)
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def place(self):
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offset = vector(0, 0)
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for inst in self.local_insts:
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inst.place(offset)
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offset = inst.rx() + 3 * self.m3_pitch
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self.height = self.local_mods[0].height
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self.width = self.local_insts[-1].rx()
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def route(self):
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# Route the global wordlines (assumes pins all line up)
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for port in self.all_ports:
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port_inputs = [x for x in self.local_mods[0].get_inputs() if "wl_{}".format(port) in x]
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for i, pin_name in enumerate(port_inputs):
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pins = [x.get_pin(pin_name) for x in self.local_insts]
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y_offset = pins[0].cy()
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if port == 0:
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y_offset -= 1.5 * self.m3_pitch
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else:
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y_offset += 1.5 * self.m3_pitch
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start_offset = vector(pins[0].lx(), y_offset)
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end_offset = vector(pins[-1].rx(), y_offset)
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self.add_layout_pin_segment_center(text=pin_name,
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layer="m3",
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start=start_offset,
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end=end_offset)
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for pin in pins:
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer="m3",
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offset=pin.center())
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end_offset = vector(pin.cx(), y_offset)
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self.add_path("m3", [pin.center(), end_offset])
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def add_layout_pins(self):
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# Regular bitlines
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for col, inst in zip(self.col_offsets, self.local_insts):
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for port in self.all_ports:
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port_inouts = [x for x in inst.mod.get_inouts() if x.startswith("bl_{}".format(port)) or x.startswith("br_{}".format(port))]
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for pin_name in port_inouts:
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# Offset of the last underscore that defines the bit number
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bit_index = pin_name.rindex('_')
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# col is the bit offset of the local array,
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# while col_value is the offset within this array
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col_value = int(pin_name[bit_index + 1:])
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# Name of signal without the bit
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base_name = pin_name[:bit_index]
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# Strip the bit and add the new one
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new_name = "{0}_{1}".format(base_name, col + col_value)
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self.copy_layout_pin(inst, pin_name, new_name)
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# Replica bitlines
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self.copy_layout_pin(self.local_insts[0], "rbl_bl_0_0")
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self.copy_layout_pin(self.local_insts[0], "rbl_br_0_0")
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if len(self.all_ports) > 1:
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self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_0")
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self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_0")
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for inst in self.insts:
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self.copy_power_pins(inst, "vdd")
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self.copy_power_pins(inst, "gnd")
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