mirror of https://github.com/VLSIDA/OpenRAM.git
45 lines
1.6 KiB
Python
45 lines
1.6 KiB
Python
import design
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import debug
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import utils
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from tech import GDS,layer
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class bitcell(design.design):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pin_names = ["BL", "BR", "WL", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("cell_6t", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "cell_6t", GDS["unit"], layer["boundary"])
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def __init__(self):
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design.design.__init__(self, "cell_6t")
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debug.info(2, "Create bitcell")
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self.width = bitcell.width
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self.height = bitcell.height
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self.pin_map = bitcell.pin_map
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def analytical_delay(self, slew, load=0, swing = 0.5):
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# delay of bit cell is not like a driver(from WL)
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# so the slew used should be 0
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# it should not be slew dependent?
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# because the value is there
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# the delay is only over half transsmission gate
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from tech import spice
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r = spice["min_tx_r"]*3
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c_para = spice["min_tx_drain_c"]
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing)
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return result
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def analytical_power(self, slew, load=0, swing = 0.5):
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#Power of the bitcell. Mostly known for leakage, but dynamic can also be factored in.
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#Only consider leakage power for now. Value defined in tech file rather than calculated.
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from tech import spice
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leakage = spice["bitcell_leakage"]
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total_power = leakage
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return total_power
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