OpenRAM

mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00

Files

T

mrg d92c7a634d Use packages for imports.

Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.

2022-07-13 15:55:57 -07:00

__init__.py

update copyright year.

2021-01-22 11:24:53 -08:00

.magicrc

Add ability to run a single unit test in docker

2021-11-03 08:32:29 -07:00

README

Rename LICENSE file to README for github license detection

2019-01-30 13:09:26 -08:00

scn4m_subm.lydrc

Add DRC rules and display files

2021-11-22 11:33:27 -08:00

scn4m_subm.lylvs

Debugging klayout for SCMOS and FreePDK45.

2021-11-22 11:33:27 -08:00

SCN4M_SUBM.20.tech

Do not extract bb (bounding box) layer in SCN4M_SUBM tech file

2022-01-13 14:39:34 -08:00

setup.tcl

Fix bitcell and pbitcell with different cell names

2020-11-03 11:30:40 -08:00

tech.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

README

The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following
license information:
---------------------------------------------------------------
Tim Edwards
Open Circuit Design
v1.0 April 2013
v1.1 May   2015
v1.2 April 2017
---------------------------------------------------------------
GPL Copyright (c) 2017