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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-04 08:44:12 +02:00
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be1c59f10cab4526836261247edfdb649fa2cc61
OpenRAM/technology/scn3me_subm
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Matt Guthaus be1c59f10c Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.
2018-02-02 12:31:33 -08:00
..
gds_lib
Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.
2018-02-02 12:31:33 -08:00
mag_lib
Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
sp_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sue_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
tech
Fix 6T and replica cell contact spacing issues with Magic DRC.
2018-01-26 12:39:00 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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