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luke
/
OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 09:30:38 +02:00
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bdda7c4f5f7bfa7e5df0646493f5d01b671776be
OpenRAM
/
compiler
/
verify
T
History
mrg
537e862d48
Add -full to LVS script
2020-11-10 20:38:41 -08:00
..
__init__.py
Temp comment Magic GDS filter code.
2020-11-10 13:37:18 -08:00
assura.py
Output DRC and LVS run files to output directory.
2020-11-09 11:12:31 -08:00
calibre.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
magic.py
Add -full to LVS script
2020-11-10 20:38:41 -08:00
none.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
run_script.py
Output DRC and LVS run files to output directory.
2020-11-09 11:12:31 -08:00
