Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells		2019-02-25 16:10:34 -08:00
..
big_config_scn4m_subm.py	Move inspect into if statement for runtime	2019-01-30 08:42:25 -08:00
example_config_1rw_1r_scn4m_subm.py	Add auto-detect of custom bitcells	2019-02-25 16:10:34 -08:00
example_config_1w_1r_scn4m_subm.py	Add auto-detect of custom bitcells	2019-02-25 16:10:34 -08:00
example_config_freepdk45.py	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
example_config_scn4m_subm.py	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
medium_config_scn4m_subm.py	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00