This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 09:30:38 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
bbffec863bd61ffe10148e6e877c35d19251ac4b
OpenRAM
/
compiler
/
bitcells
T
History
Hunter Nichols
a711a5823d
Merged dev and fix conflicts in geometry.py
2018-10-24 10:52:22 -07:00
..
bitcell_1rw_1r.py
Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.
2018-10-22 23:33:01 -07:00
bitcell.py
Merge branch 'multiport' into supply_routing
2018-10-11 09:56:38 -07:00
pbitcell.py
Updating comments and cleaning up code for pbitcell.
2018-10-21 19:10:04 -07:00
replica_bitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00