mirror of https://github.com/VLSIDA/OpenRAM.git
24 lines
846 B
Python
24 lines
846 B
Python
import design
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import debug
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import utils
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from tech import GDS,layer
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class replica_bitcell(design.design):
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"""
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A single bit cell (6T, 8T, etc.)
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pin_names = ["bl", "br", "wl", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"], layer["boundary"])
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def __init__(self):
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design.design.__init__(self, "replica_cell_6t")
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debug.info(2, "Create replica bitcell object")
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self.width = replica_bitcell.width
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self.height = replica_bitcell.height
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self.pin_map = replica_bitcell.pin_map
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