mirror of https://github.com/VLSIDA/OpenRAM.git
20 lines
408 B
Python
20 lines
408 B
Python
word_size = 2
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num_words = 16
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num_banks = 1
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tech_name = "freepdk45"
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process_corners = ["TT"]
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supply_voltages = [1.0]
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temperatures = [25]
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output_path = "temp"
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output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
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#Below are some additions to test additional ports on sram
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#bitcell = "pbitcell"
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# These are the configuration parameters
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#rw_ports = 2
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#r_ports = 2
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#w_ports = 2
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