mirror of https://github.com/VLSIDA/OpenRAM.git
20 lines
361 B
Python
20 lines
361 B
Python
word_size = 2
|
|
num_words = 16
|
|
num_banks = 1
|
|
|
|
tech_name = "freepdk45"
|
|
process_corners = ["TT"]
|
|
supply_voltages = [1.0]
|
|
temperatures = [25]
|
|
|
|
output_path = "temp"
|
|
output_name = "sram_2_16_1_freepdk45"
|
|
|
|
#Below are some additions to test additional ports on sram
|
|
#bitcell = "pbitcell"
|
|
|
|
# These are the configuration parameters
|
|
#rw_ports = 2
|
|
#r_ports = 2
|
|
#w_ports = 2
|