mirror of https://github.com/VLSIDA/OpenRAM.git
44 lines
1.7 KiB
Python
44 lines
1.7 KiB
Python
import design
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import debug
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import utils
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from tech import GDS,layer
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class sense_amp(design.design):
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"""
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This module implements the single sense amp cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library.
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Sense amplifier to read a pair of bit-lines.
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"""
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pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
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def __init__(self, name):
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design.design.__init__(self, name)
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debug.info(2, "Create sense_amp")
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self.width = sense_amp.width
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self.height = sense_amp.height
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self.pin_map = sense_amp.pin_map
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def input_load(self):
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#Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
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from tech import spice, parameter
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bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
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return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff
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def analytical_delay(self, slew, load=0.0):
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from tech import spice
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r = spice["min_tx_r"]/(10)
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c_para = spice["min_tx_drain_c"]
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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return self.return_delay(result.delay, result.slew)
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
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total_power = self.return_power()
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return total_power
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