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luke
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OpenRAM
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b8061d3a4e03684ff22d9b5fe93d87cab2a774e3
OpenRAM
/
compiler
/
bitcells
T
History
Hunter Nichols
b8061d3a4e
Added initial code for determining the logical effort delay of the wordline.
2018-11-08 23:54:18 -08:00
..
bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
bitcell.py
Added initial code for determining the logical effort delay of the wordline.
2018-11-08 23:54:18 -08:00
pbitcell.py
Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell.
2018-11-02 05:59:47 -07:00
replica_bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_bitcell.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00