mirror of https://github.com/VLSIDA/OpenRAM.git
125 lines
4.1 KiB
Python
125 lines
4.1 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram.tech import layer_properties as layer_props
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from openram import OPTS
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class wordline_buffer_array(design):
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"""
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Creates a Wordline Buffer/Inverter array
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"""
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def __init__(self, name, rows, cols):
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design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.rows = rows
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self.cols = cols
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_drivers()
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.place_drivers()
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self.route_layout()
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self.route_supplies()
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# Don't offset these because some cells use standard cell style drivers
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#self.offset_all_coordinates()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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# inputs to wordline_driver.
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for i in range(self.rows):
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self.add_pin("in_{0}".format(i), "INPUT")
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# Outputs from wordline_driver.
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for i in range(self.rows):
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self.add_pin("out_{0}".format(i), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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b = factory.create(module_type=OPTS.bitcell)
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self.wl_driver = factory.create(module_type="inv_dec",
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size=self.cols,
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height=b.height)
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def route_supplies(self):
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"""
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Add a pin for each row of vdd/gnd which
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are must-connects next level up.
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"""
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if layer_props.wordline_driver.vertical_supply:
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self.route_vertical_pins("vdd", self.wld_inst)
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self.route_vertical_pins("gnd", self.wld_inst)
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else:
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self.route_vertical_pins("vdd", self.wld_inst, xside="rx",)
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self.route_vertical_pins("gnd", self.wld_inst, xside="lx",)
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def create_drivers(self):
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self.wld_inst = []
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for row in range(self.rows):
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self.wld_inst.append(self.add_inst(name="wld{0}".format(row),
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mod=self.wl_driver))
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self.connect_inst(["in_{0}".format(row),
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"out_{0}".format(row),
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"vdd", "gnd"])
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def place_drivers(self):
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for row in range(self.rows):
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# These are flipped since we always start with an RBL on the bottom
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if (row % 2):
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y_offset = self.wl_driver.height * row
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inst_mirror = "R0"
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else:
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y_offset = self.wl_driver.height * (row + 1)
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inst_mirror = "MX"
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offset = [0, y_offset]
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self.wld_inst[row].place(offset=offset,
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mirror=inst_mirror)
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self.width = self.wl_driver.width
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self.height = self.wl_driver.height * self.rows
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def route_layout(self):
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""" Route all of the signals """
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for row in range(self.rows):
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inst = self.wld_inst[row]
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self.copy_layout_pin(inst, "A", "in_{0}".format(row))
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# output each WL on the right
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wl_offset = inst.get_pin("Z").rc()
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self.add_layout_pin_segment_center(text="out_{0}".format(row),
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layer=self.route_layer,
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start=wl_offset,
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end=wl_offset - vector(self.m1_width, 0))
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