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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-09-05 01:01:33 +02:00
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b65ebc61603aadfd64c34b91cbb1ad01f43dce54
OpenRAM
/
technology
/
scn4m_subm
/
gds_lib
T
History
Bugra Onal
7ed99278bd
Sense amp fixes
2023-04-19 12:42:02 -07:00
..
cell_1rw.gds
Move power pins to horizontal or vertical layer in all cells.
2022-03-31 16:36:19 -07:00
cell_2rw.gds
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
dff.gds
…
dummy_cell_1rw.gds
Move power pins to horizontal or vertical layer in all cells.
2022-03-31 16:36:19 -07:00
dummy_cell_2rw.gds
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
replica_cell_1rw.gds
Move power pins to horizontal or vertical layer in all cells.
2022-03-31 16:36:19 -07:00
replica_cell_2rw.gds
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
sense_amp.gds
Sense amp fixes
2023-04-19 12:42:02 -07:00
tri_gate.gds
…
write_driver.gds
…
