mirror of https://github.com/VLSIDA/OpenRAM.git
291 lines
8.1 KiB
Python
291 lines
8.1 KiB
Python
import os
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"""
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File containing the process technology parameters.
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"""
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info = {}
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info["name"] = "freepdk45"
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info["body_tie_down"] = 0
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info["has_pwell"] = True
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info["has_nwell"] = True
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#GDS file info
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GDS = {}
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GDS["unit"] = (0.0005,1e-9)
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#####################################################################################################
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##GDS Layer Map######################################################################################
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#####################################################################################################
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# create the GDS layer map
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# FIXME: parse the gds layer map from the cadence map?
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layer = {}
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layer["active"] = 1
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layer["pwell"] = 2
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layer["nwell"] = 3
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layer["nimplant"]= 4
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layer["pimplant"]= 5
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layer["vtg"] = 6
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layer["vth"] = 7
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layer["thkox"] = 8
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layer["poly"] = 9
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layer["contact"] = 10
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layer["metal1"] = 11
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layer["via1"] = 12
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layer["metal2"] = 13
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layer["via2"] = 14
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layer["metal3"] = 15
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layer["via3"] = 16
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layer["metal4"] = 17
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layer["via4"] = 18
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layer["metal5"] = 19
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layer["via5"] = 20
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layer["metal6"] = 21
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layer["via6"] = 22
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layer["metal7"] = 23
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layer["via7"] = 24
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layer["metal8"] = 25
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layer["via8"] = 26
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layer["metal9"] = 27
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layer["via9"] = 28
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layer["metal10"] = 29
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layer["text"] = 239
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layer["boundary"]= 239
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#####################################################################################################
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##END GDS Layer Map##################################################################################
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#####################################################################################################
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#####################################################################################################
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##DRC/LVS Rules Setup################################################################################
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#####################################################################################################
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#technology parameter
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parameter={}
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parameter["min_tx_size"] = 0.09
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parameter["pinv_beta"] = 3
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drclvs_home=os.environ.get("DRCLVS_HOME")
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drc={}
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#grid size
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drc["grid"] = 0.0025
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#DRC/LVS test set_up
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drc["drc_rules"]=drclvs_home+"/calibreDRC.rul"
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drc["lvs_rules"]=drclvs_home+"/calibreLVS.rul"
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drc["xrc_rules"]=drclvs_home+"/calibrexRC.rul"
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drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/layers.map"
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# minwidth_tx withcontact
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drc["minwidth_tx"]=0.09
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drc["minlength_channel"] = 0.05
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#well rules
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drc["pwell_enclose_nwell"] = 0.225
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drc["minwidth_well"] = 0.2
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#poly rules
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drc["minwidth_poly"] = 0.05
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drc["minheight_poly"] = 0.0
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drc["poly_to_poly"] = 0.14
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drc["poly_extend_active"] = 0.055
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drc["active_enclosure_gate"] = 0.07
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drc["poly_to_active"] = 0.05
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drc["poly_to_field_poly"] = 0.075
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drc["minarea_poly"] = 0.0
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#active
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drc["active_extend_gate"] = 0
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drc["active_to_body_active"] = 0.08
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drc["minwidth_active"] = 0.09
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drc["minheight_active"] = 0.09
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drc["minarea_active"] = 0
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drc["well_enclosure_active"] = 0.055
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drc["well_extend_active"] = 0.055
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#Implant
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drc["implant_to_gate"] = 0.07
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drc["implant_to_channel"] = 0.07
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drc["implant_to_contact"] = 0.025
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drc["implant_to_implant"] = 0.045
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drc["minwidth_implant"] = 0.045
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#Contact
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drc["minwidth_contact"] = 0.065
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drc["contact_to_contact"] = 0.075
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drc["active_enclosure_contact"] = 0.005
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drc["active_extend_contact"] = 0.005
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drc["poly_enclosure_contact"] = 0.005
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drc["poly_extend_contact"] = 0.005
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drc["contact_to_poly"] = 0.0375 #changed from 0.035
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#Metal1
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drc["minwidth_metal1"] = 0.065
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drc["minheight_metal1"] = 0.0
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drc["metal1_to_metal1"] = 0.065
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drc["metal1_enclosure_contact"] = 0
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drc["metal1_extend_contact"] = 0.035
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drc["metal1_extend_via1"] = 0.035
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drc["metal1_enclosure_via1"] = 0
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drc["minarea_metal1"] = 0
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#via1
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drc["minwidth_via1"] = 0.065
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drc["via1_to_via1"] = 0.075
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#Metal2
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drc["minwidth_metal2"] = 0.07
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drc["minheight_metal2"] = 0.0
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drc["metal2_to_metal2"] = 0.07
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drc["metal2_extend_via1"] = 0.035
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drc["metal2_enclosure_via1"] = 0
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drc["metal2_extend_via2"] = 0.035
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drc["metal2_enclosure_via2"] = 0
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drc["minarea_metal2"] = 0
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#Via2
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drc["minwidth_via2"] = 0.065
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drc["via2_to_via2"] = 0.075
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#Metal3
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drc["minwidth_metal3"] = 0.07
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drc["minheight_metal3"] = 0.0
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drc["metal3_to_metal3"] = 0.07
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drc["metal3_extend_via2"] = 0.035
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drc["metal3_enclosure_via2"] = 0
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drc["metal3_extend_via3"]=0.035
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drc["metal3_enclosure_via3"] = 0
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drc["minarea_metal3"] = 0
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#Via3
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drc["minwidth_via3"] = 0.065
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drc["via3_to_via3"] = 0.07
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#Metal4
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drc["minwidth_metal4"] = 0.14
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drc["minheight_metal4"] = 0.0
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drc["metal4_enclosure_via3"] = 0
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drc["metal4_extend_via3"] = 0.07
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drc["metal4_to_metal4"] = 0.14
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drc["metal4_extend_via4"] = 0.07
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drc["metal4_enclosure_via4"] = 0.07
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drc["minarea_metal4"] = 0
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#Via4
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drc["minwidth_via4"] = 0.14
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drc["via4_to_via4"] = 0.14
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#Metal5
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drc["minwidth_metal5"] = 0.14
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drc["minheight_metal5"] = 0.0
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drc["metal5_to_metal5"] = 0.14
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drc["metal5_extend_via4"] = 0.07
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drc["metal5_enclosure_via4"] = 0.07
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drc["minarea_metal5"] = 0
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#Via 5
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drc["minwidth_via5"] = 0.14
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drc["via5_to_via5"] = 0.14
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#Metal6
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drc["minwidth_metal6"] = 0.14
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drc["minheight_metal6"] = 0.0
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drc["metal6_to_metal6"] = 0.14
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drc["metal6_extend_via5"] = 0
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drc["metal6_enclosure_via5"] = 0
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#Via 6
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drc["minwidth_via6"] = 0.14
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drc["via6_to_via6"] = 0.14
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#Metal7
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drc["minwidth_metal7"] = 0.14
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drc["minheight_metal7"] = 0.0
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drc["metal7_to_metal7"] = 0.14
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drc["metal7_extend_via6"] = 0
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drc["metal7_enclosure_via6"] = 0
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#Via7
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drc["minwidth_via7"] = 0.14
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drc["via7_to_via7"] = 0.14
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#Metal8
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drc["minwidth_metal8"] = 0.14
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drc["minheight_metal8"] = 0.0
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drc["metal8_to_metal8"] = 0.14
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drc["metal8_extend_via7"] = 0
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drc["metal8_enclosure_via7"] = 0
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#Via8
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drc["minwidth_via8"] = 0.14
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drc["via8_to_via8"] = 0.14
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#Metal9
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drc["minwidth_metal9"] = 0.14
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drc["minheight_metal9"] = 0.0
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drc["metal9_to_metal9"] = 0.14
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drc["metal9_extend_via8"] = 0
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drc["metal9_enclosure_via8"] = 0
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#Via 9
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drc["minwidth_via9"] = 0.14
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drc["via9_to_via9"] = 0.14
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#Metal 10
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drc["minwidth_metal10"] = 0.14
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drc["minheight_metal10"] = 0.0
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drc["metal10_to_metal10"] = 0.14
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drc["metal10_extend_via9"] = 0
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drc["metal10_enclosure_via9"] = 0
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#####################################################################################################
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##END DRC/LVS Rules##################################################################################
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#####################################################################################################
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#####################################################################################################
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##Spice Simulation Parameters########################################################################
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#####################################################################################################
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#spice info
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spice = {}
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spice["nmos"] = "nmos_vtg"
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spice["pmos"] = "pmos_vtg"
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SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
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spice["fet_models"] = [SPICE_MODEL_DIR+"/NMOS_VTG.inc",
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SPICE_MODEL_DIR+"/PMOS_VTG.inc"]
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#spice stimulus related variables
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spice["clock_period"] = 2.0
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spice["supply_voltage"] = 1.0 #vdd in [Volts]
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spice["gnd_voltage"] = 0.0 #gnd in [Volts]
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spice["rise_time"] = 0.001 #rise time in [Nano-seconds]
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spice["fall_time"] = 0.001 #fall time in [Nano-seconds]
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spice["temp"] = 25 #temperature in [Celsius]
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#parasitics of metal for bit/word lines
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spice["bitline_res"] = 0.1 #bitline resistance in [Ohms/micro-meter]
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spice["bitline_cap"] = 0.2 #bitline capacitance in [Femto-farad/micro-meter]
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spice["wordline_res"] = 0.1 #wordline resistance in [Ohms/micro-meter]
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spice["wordline_cap"] = 0.2 #wordline capacitance in [Femto-farad/micro-meter]
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spice["FF_in_cap"] = 0.2091 #Input capacitance of ms_flop (Din) [Femto-farad]
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spice["tri_gate_out_cap"] = 0.41256 #Output capacitance of tri_gate (tri_out) [Femto-farad]
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#sram signal names
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spice["vdd_name"] = "vdd"
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spice["gnd_name"] = "gnd"
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spice["control_signals"] = ["CSb", "WEb", "OEb"]
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spice["data_name"] = "DATA"
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spice["addr_name"] = "ADDR"
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spice["pmos_name"] = spice["pmos"]
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spice["nmos_name"] = spice["nmos"]
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spice["minwidth_tx"] = drc["minwidth_tx"]
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spice["channel"] = drc["minlength_channel"]
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spice["clk"] = "clk"
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# estimated feasible period in ns
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spice["feasible_period"] = 5
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