Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

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bitcell_1rw_1r.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

bitcell_1w_1r.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

bitcell.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

pbitcell.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

replica_bitcell_1rw_1r.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

replica_bitcell_1w_1r.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

replica_bitcell.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

replica_pbitcell.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00