mirror of https://github.com/VLSIDA/OpenRAM.git
30 lines
972 B
Python
30 lines
972 B
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2020 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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class _dff:
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def __init__(self, use_custom_ports, custom_port_list, custom_type_list, clk_pin):
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self.use_custom_ports = use_custom_ports
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self.custom_port_list = custom_port_list
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self.custom_type_list = custom_type_list
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self.clk_pin = clk_pin
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class module_properties():
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"""
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TODO
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"""
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def __init__(self):
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self.names = {}
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self._dff = _dff(use_custom_ports = False,
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custom_port_list = ["D", "Q", "clk", "vdd", "gnd"],
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custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"],
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clk_pin= "clk")
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@property
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def dff(self):
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return self._dff
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