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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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b201fa4bca2a1a229d49ddba2ceea654c527a8db
OpenRAM/compiler/verify
T
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mrg e6a7ecae84 Fix missing default path in pex
2020-11-12 14:43:57 -08:00
..
__init__.py
Temp comment Magic GDS filter code.
2020-11-10 13:37:18 -08:00
assura.py
Output DRC and LVS run files to output directory.
2020-11-09 11:12:31 -08:00
calibre.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
magic.py
Fix missing default path in pex
2020-11-12 14:43:57 -08:00
none.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
run_script.py
Output DRC and LVS run files to output directory.
2020-11-09 11:12:31 -08:00
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