Michael Timothy Grimes af0756382f Merging changes and updating multiport syntax across several tests

2018-09-03 19:36:20 -07:00

..

base

Clean up GdsMill. Fix rotate bug I introduced in transFlags!

2018-08-29 15:34:45 -07:00

characterizer

Remove OEB signal since we split DIN/DOUT ports

2018-08-13 14:09:49 -07:00

gdsMill

Revert all transFlags in GdsMill

2018-08-29 17:23:04 -07:00

modules

Merging changes and updating multiport syntax across several tests

2018-09-03 19:36:20 -07:00

pgates

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00

router

Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing

2018-08-29 15:40:04 -07:00

tests

Merging changes and updating multiport syntax across several tests

2018-09-03 19:36:20 -07:00

verify

Use a .magicrc in the technology directory to read magic tech files

2018-08-30 14:20:41 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

example_config_scn3me_subm.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00

options.py

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00

sram_1bank.py

Merging changes and updating multiport syntax across several tests

2018-09-03 19:36:20 -07:00

sram_2bank.py

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00

sram_4bank.py

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00

sram_base.py

Merging changes and updating multiport syntax across several tests

2018-09-03 19:36:20 -07:00

sram_config.py

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00

sram.py

Add sram_config class. Rename port variables for better description.

2018-08-31 12:03:28 -07:00