mirror of https://github.com/VLSIDA/OpenRAM.git
137 lines
4.8 KiB
Python
137 lines
4.8 KiB
Python
import debug
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import design
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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class ms_flop_array(design.design):
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"""
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An Array of D-Flipflops used for to store Data_in & Data_out of
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Write_driver & Sense_amp, address inputs of column_mux &
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hierdecoder
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"""
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def __init__(self, columns, word_size, name=""):
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self.columns = columns
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self.word_size = word_size
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if name=="":
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name = "flop_array_c{0}_w{1}".format(columns,word_size)
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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self.words_per_row = int(self.columns / self.word_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_ms_flop_array()
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def create_layout(self):
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self.width = self.columns * self.ms.width
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self.height = self.ms.height
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self.place_ms_flop_array()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_modules(self):
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from importlib import reload
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c = reload(__import__(OPTS.ms_flop))
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self.mod_ms_flop = getattr(c, OPTS.ms_flop)
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self.ms = self.mod_ms_flop("ms_flop")
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self.add_mod(self.ms)
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def add_pins(self):
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for i in range(self.word_size):
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self.add_pin("din[{0}]".format(i))
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for i in range(self.word_size):
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self.add_pin("dout[{0}]".format(i))
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self.add_pin("dout_bar[{0}]".format(i))
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self.add_pin("clk")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_ms_flop_array(self):
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self.ms_inst={}
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for i in range(0,self.columns,self.words_per_row):
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name = "Xdff{0}".format(i)
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index = int(i/self.words_per_row)
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self.ms_inst[index]=self.add_inst(name=name,
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mod=self.ms)
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self.connect_inst(["din[{0}]".format(index),
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"dout[{0}]".format(index),
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"dout_bar[{0}]".format(index),
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"clk",
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"vdd", "gnd"])
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def place_ms_flop_array(self):
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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if (i % 2 == 0 or self.words_per_row>1):
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base = vector(i*self.ms.width,0)
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mirror = "R0"
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else:
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base = vector((i+1)*self.ms.width,0)
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mirror = "MY"
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self.ms_inst[index].place(offset=base,
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mirror=mirror)
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def add_layout_pins(self):
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for i in range(self.word_size):
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# Route both supplies
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for n in ["vdd", "gnd"]:
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for supply_pin in self.ms_inst[i].get_pins(n):
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pin_pos = supply_pin.center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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din_pins = self.ms_inst[i].get_pins("din")
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for din_pin in din_pins:
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self.add_layout_pin(text="din[{}]".format(i),
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layer=din_pin.layer,
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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dout_pin = self.ms_inst[i].get_pin("dout")
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self.add_layout_pin(text="dout[{}]".format(i),
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layer="metal2",
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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doutbar_pin = self.ms_inst[i].get_pin("dout_bar")
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self.add_layout_pin(text="dout_bar[{}]".format(i),
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layer="metal2",
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offset=doutbar_pin.ll(),
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width=doutbar_pin.width(),
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height=doutbar_pin.height())
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# Continous clk rail along with label.
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self.add_layout_pin(text="clk",
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layer="metal1",
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offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1),
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width=self.width,
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height=drc["minwidth_metal1"])
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def analytical_delay(self, slew, load=0.0):
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return self.ms.analytical_delay(slew=slew, load=load)
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