mirror of https://github.com/VLSIDA/OpenRAM.git
506 lines
24 KiB
Python
506 lines
24 KiB
Python
import os,sys,re
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import debug
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import math
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from .setup_hold import *
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from .delay import *
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from .charutils import *
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import tech
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import numpy as np
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from globals import OPTS
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class lib:
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""" lib file generation."""
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def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay):
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self.out_dir = out_dir
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self.sram = sram
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self.sp_file = sp_file
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self.use_model = use_model
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self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later.
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self.prepare_tables()
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self.create_corners()
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self.characterize_corners()
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def gen_port_names(self):
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"""Generates the port names to be written to the lib file"""
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#This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here.
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self.write_ports = []
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self.read_ports = []
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self.total_port_num = OPTS.rw_ports + OPTS.w_ports + OPTS.r_ports
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#save a member variable to avoid accessing global. readwrite ports have different control signals.
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self.readwrite_port_num = OPTS.rw_ports
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#Generate the port names. readwrite ports are required to be added first for this to work.
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for readwrite_port_num in range(OPTS.rw_ports):
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self.read_ports.append(readwrite_port_num)
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self.write_ports.append(readwrite_port_num)
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#This placement is intentional. It makes indexing input data easier. See self.data_values
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for read_port_num in range(OPTS.rw_ports, OPTS.r_ports):
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self.read_ports.append(read_port_num)
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for write_port_num in range(OPTS.rw_ports+OPTS.r_ports, OPTS.w_ports):
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self.write_ports.append(write_port_num)
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def prepare_tables(self):
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""" Determine the load/slews if they aren't specified in the config file. """
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# These are the parameters to determine the table sizes
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#self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
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self.load_scales = np.array([0.25, 1, 8])
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#self.load_scales = np.array([0.25, 1])
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self.load = tech.spice["dff_in_cap"]
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self.loads = self.load_scales*self.load
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debug.info(1,"Loads: {0}".format(self.loads))
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#self.slew_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
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self.slew_scales = np.array([0.25, 1, 8])
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#self.slew_scales = np.array([0.25, 1])
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self.slew = tech.spice["rise_time"]
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self.slews = self.slew_scales*self.slew
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debug.info(1,"Slews: {0}".format(self.slews))
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def create_corners(self):
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""" Create corners for characterization. """
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# Get the corners from the options file
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self.temperatures = OPTS.temperatures
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self.supply_voltages = OPTS.supply_voltages
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self.process_corners = OPTS.process_corners
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# Enumerate all possible corners
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self.corners = []
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self.lib_files = []
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for proc in self.process_corners:
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for temp in self.temperatures:
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for volt in self.supply_voltages:
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self.corner_name = "{0}_{1}_{2}V_{3}C".format(self.sram.name,
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proc,
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volt,
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temp)
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self.corner_name = self.corner_name.replace(".","p") # Remove decimals
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lib_name = self.out_dir+"{}.lib".format(self.corner_name)
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# A corner is a tuple of PVT
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self.corners.append((proc, volt, temp))
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self.lib_files.append(lib_name)
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def characterize_corners(self):
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""" Characterize the list of corners. """
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for (self.corner,lib_name) in zip(self.corners,self.lib_files):
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debug.info(1,"Corner: " + str(self.corner))
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(self.process, self.voltage, self.temperature) = self.corner
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self.lib = open(lib_name, "w")
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debug.info(1,"Writing to {0}".format(lib_name))
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self.characterize()
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self.lib.close()
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def characterize(self):
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""" Characterize the current corner. """
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self.compute_delay()
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self.compute_setup_hold()
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self.write_header()
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#Loop over all readwrite ports. This is debugging. Will change later.
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for port in range(self.total_port_num):
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#set the read and write port as inputs.
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self.write_data_bus(port)
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self.write_addr_bus(port)
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self.write_control_pins(port) #need to split this into sram and port control signals
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self.write_clk_timing_power(port)
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self.write_footer()
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def write_footer(self):
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""" Write the footer """
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self.lib.write("}\n")
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def write_header(self):
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""" Write the header information """
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self.lib.write("library ({0}_lib)".format(self.corner_name))
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self.lib.write("{\n")
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self.lib.write(" delay_model : \"table_lookup\";\n")
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self.write_units()
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self.write_defaults()
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self.write_LUT_templates()
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self.lib.write(" default_operating_conditions : OC; \n")
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self.write_bus()
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self.lib.write("cell ({0})".format(self.sram.name))
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self.lib.write("{\n")
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self.lib.write(" memory(){ \n")
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self.lib.write(" type : ram;\n")
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self.lib.write(" address_width : {};\n".format(self.sram.addr_size))
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self.lib.write(" word_width : {};\n".format(self.sram.word_size))
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self.lib.write(" }\n")
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self.lib.write(" interface_timing : true;\n")
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self.lib.write(" dont_use : true;\n")
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self.lib.write(" map_only : true;\n")
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self.lib.write(" dont_touch : true;\n")
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self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height))
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# Leakage is included in dynamic when macro is enabled
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self.lib.write(" leakage_power () {\n")
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self.lib.write(" when : \"CSb\";\n")
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self.lib.write(" value : {};\n".format(self.char_results["leakage_power"]))
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self.lib.write(" }\n")
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self.lib.write(" cell_leakage_power : {};\n".format(0))
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def write_units(self):
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""" Adds default units for time, voltage, current,..."""
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self.lib.write(" time_unit : \"1ns\" ;\n")
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self.lib.write(" voltage_unit : \"1v\" ;\n")
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self.lib.write(" current_unit : \"1mA\" ;\n")
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self.lib.write(" resistance_unit : \"1kohm\" ;\n")
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self.lib.write(" capacitive_load_unit(1 ,fF) ;\n")
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self.lib.write(" leakage_power_unit : \"1mW\" ;\n")
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self.lib.write(" pulling_resistance_unit :\"1kohm\" ;\n")
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self.lib.write(" operating_conditions(OC){\n")
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self.lib.write(" process : {} ;\n".format(1.0)) # How to use TT, FF, SS?
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self.lib.write(" voltage : {} ;\n".format(self.voltage))
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self.lib.write(" temperature : {};\n".format(self.temperature))
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self.lib.write(" }\n\n")
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def write_defaults(self):
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""" Adds default values for slew and capacitance."""
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self.lib.write(" input_threshold_pct_fall : 50.0 ;\n")
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self.lib.write(" output_threshold_pct_fall : 50.0 ;\n")
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self.lib.write(" input_threshold_pct_rise : 50.0 ;\n")
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self.lib.write(" output_threshold_pct_rise : 50.0 ;\n")
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self.lib.write(" slew_lower_threshold_pct_fall : 10.0 ;\n")
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self.lib.write(" slew_upper_threshold_pct_fall : 90.0 ;\n")
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self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n")
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self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n")
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self.lib.write(" nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"]))
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self.lib.write(" nom_temperature : {};\n".format(tech.spice["nom_temperature"]))
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self.lib.write(" nom_process : {};\n".format(1.0))
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self.lib.write(" default_cell_leakage_power : 0.0 ;\n")
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self.lib.write(" default_leakage_power_density : 0.0 ;\n")
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self.lib.write(" default_input_pin_cap : 1.0 ;\n")
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self.lib.write(" default_inout_pin_cap : 1.0 ;\n")
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self.lib.write(" default_output_pin_cap : 0.0 ;\n")
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self.lib.write(" default_max_transition : 0.5 ;\n")
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self.lib.write(" default_fanout_load : 1.0 ;\n")
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self.lib.write(" default_max_fanout : 4.0 ;\n")
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self.lib.write(" default_connection_class : universal ;\n\n")
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def create_list(self,values):
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""" Helper function to create quoted, line wrapped list """
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list_values = ", ".join(str(v) for v in values)
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return "\"{0}\"".format(list_values)
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def create_array(self,values, length):
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""" Helper function to create quoted, line wrapped array with each row of given length """
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# check that the length is a multiple or give an error!
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debug.check(len(values)%length == 0,"Values are not a multiple of the length. Cannot make a full array.")
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rounded_values = list(map(round_time,values))
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split_values = [rounded_values[i:i+length] for i in range(0, len(rounded_values), length)]
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formatted_rows = list(map(self.create_list,split_values))
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formatted_array = ",\\\n".join(formatted_rows)
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return formatted_array
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def write_index(self, number, values):
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""" Write the index """
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quoted_string = self.create_list(values)
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self.lib.write(" index_{0}({1});\n".format(number,quoted_string))
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def write_values(self, values, row_length, indent):
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""" Write the index """
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quoted_string = self.create_array(values, row_length)
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# indent each newline plus extra spaces for word values
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indented_string = quoted_string.replace('\n', '\n' + indent +" ")
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self.lib.write("{0}values({1});\n".format(indent,indented_string))
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def write_LUT_templates(self):
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""" Adds lookup_table format (A 1x1 lookup_table)."""
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Tran = ["CELL_TABLE"]
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for i in Tran:
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self.lib.write(" lu_table_template({0})".format(i))
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self.lib.write("{\n")
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self.lib.write(" variable_1 : input_net_transition;\n")
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self.lib.write(" variable_2 : total_output_net_capacitance;\n")
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self.write_index(1,self.slews)
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self.write_index(2,self.loads)
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self.lib.write(" }\n\n")
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CONS = ["CONSTRAINT_TABLE"]
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for i in CONS:
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self.lib.write(" lu_table_template({0})".format(i))
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self.lib.write("{\n")
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self.lib.write(" variable_1 : related_pin_transition;\n")
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self.lib.write(" variable_2 : constrained_pin_transition;\n")
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self.write_index(1,self.slews)
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self.write_index(2,self.slews)
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self.lib.write(" }\n\n")
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# self.lib.write(" lu_table_template(CLK_TRAN) {\n")
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# self.lib.write(" variable_1 : constrained_pin_transition;\n")
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# self.write_index(1,self.slews)
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# self.lib.write(" }\n\n")
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# self.lib.write(" lu_table_template(TRAN) {\n")
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# self.lib.write(" variable_1 : total_output_net_capacitance;\n")
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# self.write_index(1,self.slews)
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# self.lib.write(" }\n\n")
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# CONS2 = ["INPUT_BY_TRANS_FOR_CLOCK" , "INPUT_BY_TRANS_FOR_SIGNAL"]
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# for i in CONS2:
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# self.lib.write(" power_lut_template({0})".format(i))
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# self.lib.write("{\n")
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# self.lib.write(" variable_1 : input_transition_time;\n")
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# #self.write_index(1,self.slews)
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# self.write_index(1,[self.slews[0]])
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# self.lib.write(" }\n\n")
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def write_bus(self):
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""" Adds format of DATA and ADDR bus."""
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self.lib.write("\n\n")
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self.lib.write(" type (DATA){\n")
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.sram.word_size))
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self.lib.write(" bit_from : 0;\n")
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self.lib.write(" bit_to : {0};\n".format(self.sram.word_size - 1))
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self.lib.write(" }\n\n")
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self.lib.write(" type (ADDR){\n")
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.sram.addr_size))
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self.lib.write(" bit_from : 0;\n")
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self.lib.write(" bit_to : {0};\n".format(self.sram.addr_size - 1))
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self.lib.write(" }\n\n")
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def write_FF_setuphold(self):
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""" Adds Setup and Hold timing results"""
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type : setup_rising; \n")
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" rise_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = list(map(round_time,self.times["setup_times_LH"]))
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" fall_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = list(map(round_time,self.times["setup_times_HL"]))
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type : hold_rising; \n")
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" rise_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = list(map(round_time,self.times["hold_times_LH"]))
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" fall_constraint(CONSTRAINT_TABLE) {\n")
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rounded_values = list(map(round_time,self.times["hold_times_HL"]))
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self.write_values(rounded_values,len(self.slews)," ")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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def write_data_bus_output(self, read_port):
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""" Adds data bus timing results."""
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self.lib.write(" bus(DOUT{0}){{\n".format(read_port))
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self.lib.write(" bus_type : DATA; \n")
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self.lib.write(" direction : output; \n")
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# This is conservative, but limit to range that we characterized.
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self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads)))
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self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads)))
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self.lib.write(" memory_read(){ \n")
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self.lib.write(" address : ADDR; \n")
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self.lib.write(" }\n")
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self.lib.write(" pin(DOUT{1}[{0}:0]){{\n".format(self.sram.word_size - 1, read_port))
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self.write_FF_setuphold()
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_sense : non_unate; \n")
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" timing_type : rising_edge; \n")
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self.lib.write(" cell_rise(CELL_TABLE) {\n")
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self.write_values(self.char_results["delay_lh{0}".format(read_port)],len(self.loads)," ")
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self.lib.write(" }\n") # rise delay
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self.lib.write(" cell_fall(CELL_TABLE) {\n")
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self.write_values(self.char_results["delay_hl{0}".format(read_port)],len(self.loads)," ")
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self.lib.write(" }\n") # fall delay
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self.lib.write(" rise_transition(CELL_TABLE) {\n")
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self.write_values(self.char_results["slew_lh{0}".format(read_port)],len(self.loads)," ")
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self.lib.write(" }\n") # rise trans
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self.lib.write(" fall_transition(CELL_TABLE) {\n")
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self.write_values(self.char_results["slew_hl{0}".format(read_port)],len(self.loads)," ")
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self.lib.write(" }\n") # fall trans
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self.lib.write(" }\n") # timing
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self.lib.write(" }\n") # pin
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self.lib.write(" }\n\n") # bus
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def write_data_bus_input(self, write_port):
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""" Adds data bus timing results."""
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self.lib.write(" bus(DIN{0}){{\n".format(write_port))
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self.lib.write(" bus_type : DATA; \n")
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self.lib.write(" direction : input; \n")
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# This is conservative, but limit to range that we characterized.
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self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads)))
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self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads)))
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self.lib.write(" memory_write(){ \n")
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self.lib.write(" address : ADDR; \n")
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self.lib.write(" clocked_on : clk; \n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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def write_data_bus(self, port):
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""" Adds data bus timing results."""
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if port in self.write_ports:
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self.write_data_bus_input(port)
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if port in self.read_ports:
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self.write_data_bus_output(port)
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def write_addr_bus(self, port):
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""" Adds addr bus timing results."""
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self.lib.write(" bus(ADDR{0}){{\n".format(port))
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self.lib.write(" bus_type : ADDR; \n")
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self.lib.write(" direction : input; \n")
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self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
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self.lib.write(" max_transition : {0};\n".format(self.slews[-1]))
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self.lib.write(" pin(ADDR{1}[{0}:0])".format(self.sram.addr_size - 1, port))
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self.lib.write("{\n")
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self.write_FF_setuphold()
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self.lib.write(" }\n")
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self.lib.write(" }\n\n")
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def write_control_pins(self, port):
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""" Adds control pins timing results."""
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#The control pins are still to be determined. This is a placeholder for what could be.
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ctrl_pin_names = ["CSb"]
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if port in self.write_ports and port in self.read_ports:
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ctrl_pin_names.append("WEb")
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for i in ctrl_pin_names:
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self.lib.write(" pin({0}{1})".format(i,port))
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self.lib.write("{\n")
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self.lib.write(" direction : input; \n")
|
|
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
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|
self.write_FF_setuphold()
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|
self.lib.write(" }\n\n")
|
|
|
|
#Port is a temporary input here. I do need a way to dynamically write the control signal here though.
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|
def write_clk_timing_power(self, port):
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""" Adds clk pin timing results."""
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|
|
|
self.lib.write(" pin(clk){\n")
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|
self.lib.write(" clock : true;\n")
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|
self.lib.write(" direction : input; \n")
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|
# FIXME: This depends on the clock buffer size in the control logic
|
|
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
|
|
|
|
# Find the average power of 1 and 0 bits for writes and reads over all loads/slews
|
|
# Could make it a table, but this is fine for now.
|
|
avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)])
|
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avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)])
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|
|
|
# Equally divide read/write power between first and second half of clock period
|
|
self.lib.write(" internal_power(){\n")
|
|
self.lib.write(" when : \"!CSb & clk & !WEb\"; \n")
|
|
self.lib.write(" rise_power(scalar){\n")
|
|
self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" fall_power(scalar){\n")
|
|
self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" }\n")
|
|
|
|
self.lib.write(" internal_power(){\n")
|
|
self.lib.write(" when : \"!CSb & !clk & WEb\"; \n")
|
|
self.lib.write(" rise_power(scalar){\n")
|
|
self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" fall_power(scalar){\n")
|
|
self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" }\n")
|
|
# Have 0 internal power when disabled, this will be represented as leakage power.
|
|
self.lib.write(" internal_power(){\n")
|
|
self.lib.write(" when : \"CSb\"; \n")
|
|
self.lib.write(" rise_power(scalar){\n")
|
|
self.lib.write(" values(\"0\");\n")
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" fall_power(scalar){\n")
|
|
self.lib.write(" values(\"0\");\n")
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" }\n")
|
|
|
|
min_pulse_width = round_time(self.char_results["min_period"])/2.0
|
|
min_period = round_time(self.char_results["min_period"])
|
|
self.lib.write(" timing(){ \n")
|
|
self.lib.write(" timing_type :\"min_pulse_width\"; \n")
|
|
self.lib.write(" related_pin : clk; \n")
|
|
self.lib.write(" rise_constraint(scalar) {\n")
|
|
self.lib.write(" values(\"{0}\"); \n".format(min_pulse_width))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" fall_constraint(scalar) {\n")
|
|
self.lib.write(" values(\"{0}\"); \n".format(min_pulse_width))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" timing(){ \n")
|
|
self.lib.write(" timing_type :\"minimum_period\"; \n")
|
|
self.lib.write(" related_pin : clk; \n")
|
|
self.lib.write(" rise_constraint(scalar) {\n")
|
|
self.lib.write(" values(\"{0}\"); \n".format(min_period))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" fall_constraint(scalar) {\n")
|
|
self.lib.write(" values(\"{0}\"); \n".format(min_period))
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" }\n")
|
|
self.lib.write(" }\n")
|
|
|
|
def compute_delay(self):
|
|
""" Do the analysis if we haven't characterized the SRAM yet """
|
|
if not hasattr(self,"d"):
|
|
self.d = delay(self.sram, self.sp_file, self.corner)
|
|
if self.use_model:
|
|
self.char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
|
|
else:
|
|
#Temporary Workaround to here to set # of ports. Crashes if set in config file.
|
|
#OPTS.rw_ports = 0
|
|
#OPTS.r_ports = 1
|
|
#OPTS.w_ports = 1
|
|
|
|
probe_address = "1" * self.sram.addr_size
|
|
probe_data = self.sram.word_size - 1
|
|
self.char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
|
|
|
|
|
|
def compute_setup_hold(self):
|
|
""" Do the analysis if we haven't characterized a FF yet """
|
|
# Do the analysis if we haven't characterized a FF yet
|
|
if not hasattr(self,"sh"):
|
|
self.sh = setup_hold(self.corner)
|
|
if self.use_model:
|
|
self.times = self.sh.analytical_setuphold(self.slews,self.loads)
|
|
else:
|
|
self.times = self.sh.analyze(self.slews,self.slews)
|
|
|