mirror of https://github.com/VLSIDA/OpenRAM.git
293 lines
12 KiB
Python
293 lines
12 KiB
Python
import debug
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import design
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import math
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from tech import drc
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import contact
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from pinv import pinv
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from vector import vector
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from globals import OPTS
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from pnand2 import pnand2
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from pnand3 import pnand3
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class hierarchical_predecode(design.design):
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"""
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Pre 2x4 and 3x8 decoder shared code.
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"""
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def __init__(self, input_number):
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self.number_of_inputs = input_number
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self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
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design.design.__init__(self, name="pre{0}x{1}".format(self.number_of_inputs,self.number_of_outputs))
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell_height = self.mod_bitcell.height
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def add_pins(self):
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for k in range(self.number_of_inputs):
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self.add_pin("in[{0}]".format(k))
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for i in range(self.number_of_outputs):
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self.add_pin("out[{0}]".format(i))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_modules(self):
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""" Create the INV and NAND gate """
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self.inv = pinv()
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self.add_mod(self.inv)
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self.create_nand(self.number_of_inputs)
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self.add_mod(self.nand)
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def create_nand(self,inputs):
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""" Create the NAND for the predecode input stage """
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if inputs==2:
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self.nand = pnand2()
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elif inputs==3:
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self.nand = pnand3()
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else:
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debug.error("Invalid number of predecode inputs.",-1)
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def setup_constraints(self):
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# we are going to use horizontal vias, so use the via height
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# use a conservative douple spacing just to get rid of annoying via DRCs
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self.m2_pitch = contact.m1m2.height + 2*self.m2_space
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# The rail offsets are indexed by the label
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self.rails = {}
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# Non inverted input rails
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for rail_index in range(self.number_of_inputs):
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xoffset = rail_index * self.m2_pitch + 0.5*self.m2_width
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self.rails["in[{}]".format(rail_index)]=xoffset
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# x offset for input inverters
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self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch
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# Creating the right hand side metal2 rails for output connections
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for rail_index in range(2 * self.number_of_inputs):
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xoffset = self.x_off_inv_1 + self.inv.width + ((rail_index+1) * self.m2_pitch) + 0.5*self.m2_width
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if rail_index < self.number_of_inputs:
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self.rails["Abar[{}]".format(rail_index)]=xoffset
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else:
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self.rails["A[{}]".format(rail_index-self.number_of_inputs)]=xoffset
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# x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch
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self.x_off_nand = self.x_off_inv_1 + self.inv.width + (1 + 2*self.number_of_inputs) * self.m2_pitch
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# x offset to output inverters
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self.x_off_inv_2 = self.x_off_nand + self.nand.width
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# Height width are computed
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self.width = self.x_off_inv_2 + self.inv.width
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self.height = self.number_of_outputs * self.nand.height
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def create_rails(self):
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""" Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """
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for label in self.rails.keys():
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# these are not primary inputs, so they shouldn't have a
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# label or LVS complains about different names on one net
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if label.startswith("in"):
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self.add_layout_pin(text=label,
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layer="metal2",
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offset=vector(self.rails[label] - 0.5*self.m2_width, 0),
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width=self.m2_width,
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height=self.height - 2*self.m2_space)
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else:
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self.add_rect(layer="metal2",
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offset=vector(self.rails[label] - 0.5*self.m2_width, 0),
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width=self.m2_width,
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height=self.height - 2*self.m2_space)
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def add_input_inverters(self):
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""" Create the input inverters to invert input signals for the decode stage. """
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self.in_inst = []
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for inv_num in range(self.number_of_inputs):
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name = "Xpre_inv[{0}]".format(inv_num)
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if (inv_num % 2 == 0):
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y_off = inv_num * (self.inv.height)
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mirror = "R0"
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else:
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y_off = (inv_num + 1) * (self.inv.height)
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mirror="MX"
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offset = vector(self.x_off_inv_1, y_off)
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self.in_inst.append(self.add_inst(name=name,
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mod=self.inv,
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offset=offset,
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mirror=mirror))
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self.connect_inst(["in[{0}]".format(inv_num),
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"inbar[{0}]".format(inv_num),
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"vdd", "gnd"])
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def add_output_inverters(self):
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""" Create inverters for the inverted output decode signals. """
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self.inv_inst = []
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for inv_num in range(self.number_of_outputs):
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name = "Xpre_nand_inv[{}]".format(inv_num)
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if (inv_num % 2 == 0):
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y_off = inv_num * self.inv.height
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mirror = "R0"
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else:
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y_off =(inv_num + 1)*self.inv.height
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mirror = "MX"
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offset = vector(self.x_off_inv_2, y_off)
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self.inv_inst.append(self.add_inst(name=name,
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mod=self.inv,
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offset=offset,
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mirror=mirror))
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self.connect_inst(["Z[{}]".format(inv_num),
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"out[{}]".format(inv_num),
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"vdd", "gnd"])
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def add_nand(self,connections):
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""" Create the NAND stage for the decodes """
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self.nand_inst = []
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for nand_input in range(self.number_of_outputs):
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inout = str(self.number_of_inputs)+"x"+str(self.number_of_outputs)
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name = "Xpre{0}_nand[{1}]".format(inout,nand_input)
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if (nand_input % 2 == 0):
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y_off = nand_input * self.inv.height
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mirror = "R0"
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else:
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y_off = (nand_input + 1) * self.inv.height
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mirror = "MX"
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offset = vector(self.x_off_nand, y_off)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand,
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offset=offset,
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mirror=mirror))
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self.connect_inst(connections[nand_input])
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def route(self):
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self.route_input_inverters()
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self.route_inputs_to_rails()
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self.route_nand_to_rails()
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self.route_output_inverters()
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self.route_vdd_gnd()
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def route_inputs_to_rails(self):
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""" Route the uninverted inputs to the second set of rails """
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for num in range(self.number_of_inputs):
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# route one signal next to each vdd/gnd rail since this is
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# typically where the p/n devices are and there are no
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# pins in the nand gates.
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y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1m2.width + self.m1_space
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in_pin = "in[{}]".format(num)
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a_pin = "A[{}]".format(num)
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in_pos = vector(self.rails[in_pin],y_offset)
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a_pos = vector(self.rails[a_pin],y_offset)
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self.add_path("metal1",[in_pos, a_pos])
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self.add_via_center(layers = ("metal1", "via1", "metal2"),
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offset=[self.rails[in_pin], y_offset],
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rotate=90)
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self.add_via_center(layers = ("metal1", "via1", "metal2"),
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offset=[self.rails[a_pin], y_offset],
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rotate=90)
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def route_output_inverters(self):
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"""
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Route all conections of the outputs inverters
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"""
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for num in range(self.number_of_outputs):
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# route nand output to output inv input
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zr_pos = self.nand_inst[num].get_pin("Z").rc()
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al_pos = self.inv_inst[num].get_pin("A").lc()
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# ensure the bend is in the middle
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mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y)
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mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y)
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self.add_path("metal1", [zr_pos, mid1_pos, mid2_pos, al_pos])
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z_pos = self.inv_inst[num].get_pin("Z").rc()
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self.add_layout_pin_center_segment(text="out[{}]".format(num),
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layer="metal1",
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start=z_pos,
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end=z_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(),0))
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def route_input_inverters(self):
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"""
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Route all conections of the inputs inverters [Inputs, outputs, vdd, gnd]
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"""
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for inv_num in range(self.number_of_inputs):
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out_pin = "Abar[{}]".format(inv_num)
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in_pin = "in[{}]".format(inv_num)
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#add output so that it is just below the vdd or gnd rail
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# since this is where the p/n devices are and there are no
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# pins in the nand gates.
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y_offset = (inv_num+1) * self.inv.height - 3*self.m1_space
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inv_out_pos = self.in_inst[inv_num].get_pin("Z").rc()
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right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0)
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rail_pos = vector(self.rails[out_pin],y_offset)
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self.add_path("metal1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
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self.add_via_center(layers = ("metal1", "via1", "metal2"),
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offset=rail_pos,
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rotate=90)
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#route input
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inv_in_pos = self.in_inst[inv_num].get_pin("A").lc()
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in_pos = vector(self.rails[in_pin],inv_in_pos.y)
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self.add_path("metal1", [in_pos, inv_in_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=in_pos,
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rotate=90)
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def route_nand_to_rails(self):
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# This 2D array defines the connection mapping
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nand_input_line_combination = self.get_nand_input_line_combination()
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for k in range(self.number_of_outputs):
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# create x offset list
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index_lst= nand_input_line_combination[k]
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if self.number_of_inputs == 2:
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gate_lst = ["B","A"]
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else:
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gate_lst = ["C","B","A"]
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# this will connect pins A,B or A,B,C
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for rail_pin,gate_pin in zip(index_lst,gate_lst):
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pin_pos = self.nand_inst[k].get_pin(gate_pin).lc()
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rail_pos = vector(self.rails[rail_pin], pin_pos.y)
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self.add_path("metal1", [rail_pos, pin_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=rail_pos,
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rotate=90)
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def route_vdd_gnd(self):
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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for num in range(0,self.number_of_outputs):
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# this will result in duplicate polygons for rails, but who cares
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# use the inverter offset even though it will be the nand's too
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(gate_offset, y_dir) = self.get_gate_offset(0, self.inv.height, num)
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# route vdd
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vdd_offset = self.nand_inst[num].get_pin("vdd").ll().scale(0,1)
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_offset,
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width=self.inv_inst[num].rx())
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# route gnd
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gnd_offset = self.nand_inst[num].get_pin("gnd").ll().scale(0,1)
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_offset,
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width=self.inv_inst[num].rx())
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