mirror of https://github.com/VLSIDA/OpenRAM.git
668 lines
28 KiB
Python
668 lines
28 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import sys
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from tech import drc, parameter
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import debug
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import design
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class port_data(design.design):
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"""
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Create the data port (column mux, sense amps, write driver, etc.) for the given port number.
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Port 0 always has the RBL on the left while port 1 is on the right.
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"""
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def __init__(self, sram_config, port, name=""):
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sram_config.set_local_config(self)
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self.port = port
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if self.write_size is not None:
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self.num_wmasks = int(self.word_size/self.write_size)
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else:
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self.num_wmasks = 0
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if name == "":
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name = "port_data_{0}".format(self.port)
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design.design.__init__(self, name)
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debug.info(2, "create data port of size {0} with {1} words per row".format(self.word_size,self.words_per_row))
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self.create_netlist()
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if not OPTS.netlist_only:
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debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.")
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self.create_layout()
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self.add_boundary()
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def create_netlist(self):
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self.precompute_constants()
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self.add_pins()
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self.add_modules()
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self.create_instances()
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def create_instances(self):
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if self.precharge_array:
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self.create_precharge_array()
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else:
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self.precharge_array_inst = None
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if self.sense_amp_array:
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self.create_sense_amp_array()
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else:
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self.sense_amp_array_inst = None
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if self.write_driver_array:
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self.create_write_driver_array()
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if self.write_size is not None:
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self.create_write_mask_and_array()
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else:
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self.write_mask_and_array_inst = None
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else:
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self.write_driver_array_inst = None
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self.write_mask_and_array_inst = None
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if self.column_mux_array:
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self.create_column_mux_array()
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else:
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self.column_mux_array_inst = None
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def create_layout(self):
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self.compute_instance_offsets()
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self.place_instances()
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self.route_layout()
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self.DRC_LVS()
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def add_pins(self):
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""" Adding pins for port address module"""
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self.add_pin("rbl_bl","INOUT")
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self.add_pin("rbl_br","INOUT")
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for bit in range(self.num_cols):
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self.add_pin("{0}_{1}".format(self.bl_names[self.port], bit),"INOUT")
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self.add_pin("{0}_{1}".format(self.br_names[self.port], bit),"INOUT")
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if self.port in self.read_ports:
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for bit in range(self.word_size):
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self.add_pin("dout_{}".format(bit),"OUTPUT")
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if self.port in self.write_ports:
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for bit in range(self.word_size):
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self.add_pin("din_{}".format(bit),"INPUT")
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# Will be empty if no col addr lines
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sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)]
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for pin_name in sel_names:
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self.add_pin(pin_name,"INPUT")
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if self.port in self.read_ports:
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self.add_pin("s_en", "INPUT")
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self.add_pin("p_en_bar", "INPUT")
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if self.port in self.write_ports:
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self.add_pin("w_en", "INPUT")
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for bit in range(self.num_wmasks):
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self.add_pin("bank_wmask_{}".format(bit),"INPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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def route_layout(self):
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""" Create routing among the modules """
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self.route_data_lines()
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self.route_layout_pins()
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self.route_supplies()
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def route_layout_pins(self):
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""" Add the pins """
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self.route_bitline_pins()
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self.route_control_pins()
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def route_data_lines(self):
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""" Route the bitlines depending on the port type rw, w, or r. """
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if self.port in self.readwrite_ports:
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# (write_mask_and ->) write_driver -> sense_amp -> (column_mux ->) precharge -> bitcell_array
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self.route_write_mask_and_array_in(self.port)
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self.route_write_mask_and_array_to_write_driver(self.port)
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self.route_write_driver_in(self.port)
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self.route_sense_amp_out(self.port)
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self.route_write_driver_to_sense_amp(self.port)
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self.route_sense_amp_to_column_mux_or_precharge_array(self.port)
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self.route_column_mux_to_precharge_array(self.port)
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elif self.port in self.read_ports:
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# sense_amp -> (column_mux) -> precharge -> bitcell_array
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self.route_sense_amp_out(self.port)
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self.route_sense_amp_to_column_mux_or_precharge_array(self.port)
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self.route_column_mux_to_precharge_array(self.port)
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else:
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# (write_mask_and ->) write_driver -> (column_mux ->) precharge -> bitcell_array
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self.route_write_mask_and_array_in(self.port)
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self.route_write_mask_and_array_to_write_driver(self.port)
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self.route_write_driver_in(self.port)
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self.route_write_driver_to_column_mux_or_precharge_array(self.port)
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self.route_column_mux_to_precharge_array(self.port)
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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for inst in self.insts:
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self.copy_power_pins(inst,"vdd")
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self.copy_power_pins(inst,"gnd")
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def add_modules(self):
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# Extra column +1 is for RBL
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# Precharge will be shifted left if needed
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self.precharge_array = factory.create(module_type="precharge_array",
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columns=self.num_cols + 1,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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self.add_mod(self.precharge_array)
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if self.port in self.read_ports:
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self.sense_amp_array = factory.create(module_type="sense_amp_array",
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word_size=self.word_size,
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words_per_row=self.words_per_row)
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self.add_mod(self.sense_amp_array)
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else:
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self.sense_amp_array = None
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if self.col_addr_size > 0:
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self.column_mux_array = factory.create(module_type="column_mux_array",
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columns=self.num_cols,
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word_size=self.word_size,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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self.add_mod(self.column_mux_array)
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else:
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self.column_mux_array = None
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if self.port in self.write_ports:
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self.write_driver_array = factory.create(module_type="write_driver_array",
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columns=self.num_cols,
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word_size=self.word_size,
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write_size=self.write_size)
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self.add_mod(self.write_driver_array)
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if self.write_size is not None:
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self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
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columns=self.num_cols,
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word_size=self.word_size,
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write_size=self.write_size,
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port = self.port)
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self.add_mod(self.write_mask_and_array)
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else:
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self.write_mask_and_array = None
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else:
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self.write_driver_array = None
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self.write_mask_and_array = None
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def precompute_constants(self):
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""" Get some preliminary data ready """
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# The central bus is the column address (one hot) and row address (binary)
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if self.col_addr_size>0:
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self.num_col_addr_lines = 2**self.col_addr_size
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else:
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self.num_col_addr_lines = 0
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# A space for wells or jogging m2 between modules
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self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"),
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3*self.m2_pitch)
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# create arrays of bitline and bitline_bar names for read, write, or all ports
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self.bitcell = factory.create(module_type="bitcell")
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self.bl_names = self.bitcell.get_all_bl_names()
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self.br_names = self.bitcell.get_all_br_names()
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self.wl_names = self.bitcell.get_all_wl_names()
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def create_precharge_array(self):
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""" Creating Precharge """
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if not self.precharge_array:
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self.precharge_array_inst = None
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return
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self.precharge_array_inst = self.add_inst(name="precharge_array{}".format(self.port),
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mod=self.precharge_array)
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temp = []
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# Use left BLs for RBL
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if self.port==0:
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temp.append("rbl_bl")
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temp.append("rbl_br")
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for bit in range(self.num_cols):
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temp.append(self.bl_names[self.port]+"_{0}".format(bit))
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temp.append(self.br_names[self.port]+"_{0}".format(bit))
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# Use right BLs for RBL
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if self.port==1:
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temp.append("rbl_bl")
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temp.append("rbl_br")
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temp.extend(["p_en_bar", "vdd"])
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self.connect_inst(temp)
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def place_precharge_array(self, offset):
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""" Placing Precharge """
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self.precharge_array_inst.place(offset=offset, mirror="MX")
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def create_column_mux_array(self):
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""" Creating Column Mux when words_per_row > 1 . """
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self.column_mux_array_inst = self.add_inst(name="column_mux_array{}".format(self.port),
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mod=self.column_mux_array)
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temp = []
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for col in range(self.num_cols):
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temp.append(self.bl_names[self.port]+"_{0}".format(col))
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temp.append(self.br_names[self.port]+"_{0}".format(col))
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for word in range(self.words_per_row):
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temp.append("sel_{}".format(word))
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for bit in range(self.word_size):
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temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
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temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
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temp.append("gnd")
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self.connect_inst(temp)
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def place_column_mux_array(self, offset):
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""" Placing Column Mux when words_per_row > 1 . """
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if self.col_addr_size == 0:
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return
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self.column_mux_array_inst.place(offset=offset, mirror="MX")
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def create_sense_amp_array(self):
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""" Creating Sense amp """
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self.sense_amp_array_inst = self.add_inst(name="sense_amp_array{}".format(self.port),
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mod=self.sense_amp_array)
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temp = []
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for bit in range(self.word_size):
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temp.append("dout_{}".format(bit))
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if self.words_per_row == 1:
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temp.append(self.bl_names[self.port]+"_{0}".format(bit))
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temp.append(self.br_names[self.port]+"_{0}".format(bit))
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else:
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temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
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temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
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temp.extend(["s_en", "vdd", "gnd"])
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self.connect_inst(temp)
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def place_sense_amp_array(self, offset):
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""" Placing Sense amp """
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self.sense_amp_array_inst.place(offset=offset, mirror="MX")
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def create_write_driver_array(self):
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""" Creating Write Driver """
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self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port),
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mod=self.write_driver_array)
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temp = []
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for bit in range(self.word_size):
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temp.append("din_{}".format(bit))
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for bit in range(self.word_size):
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if (self.words_per_row == 1):
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temp.append(self.bl_names[self.port] + "_{0}".format(bit))
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temp.append(self.br_names[self.port] + "_{0}".format(bit))
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else:
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temp.append(self.bl_names[self.port] + "_out_{0}".format(bit))
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temp.append(self.br_names[self.port] + "_out_{0}".format(bit))
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if self.write_size is not None:
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for i in range(self.num_wmasks):
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temp.append("wdriver_sel_{}".format(i))
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else:
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temp.append("w_en")
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def place_write_driver_array(self, offset):
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""" Placing Write Driver """
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self.write_driver_array_inst.place(offset=offset, mirror="MX")
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def create_write_mask_and_array(self):
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""" Creating Write Mask AND Array """
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self.write_mask_and_array_inst = self.add_inst(name="write_mask_and_array{}".format(self.port),
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mod=self.write_mask_and_array)
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temp = []
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for bit in range(self.num_wmasks):
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temp.append("bank_wmask_{}".format(bit))
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temp.extend(["w_en"])
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for bit in range(self.num_wmasks):
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temp.append("wdriver_sel_{}".format(bit))
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def place_write_mask_and_array(self, offset):
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""" Placing Write Mask AND array """
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self.write_mask_and_array_inst.place(offset=offset, mirror="MX")
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def compute_instance_offsets(self):
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"""
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Compute the empty instance offsets for port0 and port1 (if needed)
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"""
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vertical_port_order = []
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vertical_port_order.append(self.precharge_array_inst)
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vertical_port_order.append(self.column_mux_array_inst)
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vertical_port_order.append(self.sense_amp_array_inst)
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vertical_port_order.append(self.write_driver_array_inst)
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vertical_port_order.append(self.write_mask_and_array_inst)
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# Add one column for the the RBL
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if self.port==0:
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x_offset = self.bitcell.width
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else:
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x_offset = 0
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vertical_port_offsets = 5 * [None]
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self.width = x_offset
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self.height = 0
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for i, p in enumerate(vertical_port_order):
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if p == None:
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continue
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self.height += (p.height + self.m2_gap)
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self.width = max(self.width, p.width)
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vertical_port_offsets[i] = vector(x_offset, self.height)
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# Reversed order
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self.write_mask_and_offset = vertical_port_offsets[4]
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self.write_driver_offset = vertical_port_offsets[3]
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self.sense_amp_offset = vertical_port_offsets[2]
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self.column_mux_offset = vertical_port_offsets[1]
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self.precharge_offset = vertical_port_offsets[0]
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# Shift the precharge left if port 0
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if self.precharge_offset and self.port == 0:
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self.precharge_offset -= vector(x_offset, 0)
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def place_instances(self):
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""" Place the instances. """
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# These are fixed in the order: write mask ANDs, write driver, sense amp, column mux, precharge,
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# even if the item is not used in a given port (it will be None then)
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if self.write_mask_and_offset:
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self.place_write_mask_and_array(self.write_mask_and_offset)
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if self.write_driver_offset:
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self.place_write_driver_array(self.write_driver_offset)
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if self.sense_amp_offset:
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self.place_sense_amp_array(self.sense_amp_offset)
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if self.precharge_offset:
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self.place_precharge_array(self.precharge_offset)
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if self.column_mux_offset:
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self.place_column_mux_array(self.column_mux_offset)
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def route_sense_amp_out(self, port):
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""" Add pins for the sense amp output """
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for bit in range(self.word_size):
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data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(bit))
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self.add_layout_pin_rect_center(text="dout_{0}".format(bit),
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layer=data_pin.layer,
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width())
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def route_write_driver_in(self, port):
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""" Connecting write driver """
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for row in range(self.word_size):
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data_name = "data_{}".format(row)
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din_name = "din_{}".format(row)
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self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
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def route_write_mask_and_array_in(self, port):
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""" Add pins for the write mask and array input """
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for bit in range(self.num_wmasks):
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wmask_in_name = "wmask_in_{}".format(bit)
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bank_wmask_name = "bank_wmask_{}".format(bit)
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self.copy_layout_pin(self.write_mask_and_array_inst, wmask_in_name, bank_wmask_name)
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def route_write_mask_and_array_to_write_driver(self,port):
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""" Routing of wdriver_sel_{} between write mask AND array and write driver array. Adds layout pin for write
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mask AND array output and via for write driver enable """
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inst1 = self.write_mask_and_array_inst
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inst2 = self.write_driver_array_inst
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loc = 0
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for bit in range(self.num_wmasks):
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# Bring write mask AND array output pin to port data level
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self.copy_layout_pin(inst1, "wmask_out_{0}".format(bit), "wdriver_sel_{0}".format(bit))
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wmask_out_pin = inst1.get_pin("wmask_out_{0}".format(bit))
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wdriver_en_pin = inst2.get_pin("en_{0}".format(bit))
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# The metal2 wdriver_sel_{} wire must hit the en_{} pin after the closest bitline pin that's right of the
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# the wdriver_sel_{} pin in the write driver AND array.
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if bit == 0:
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# When the write mask output pin is right of the bitline, the target is found
|
|
while (wmask_out_pin.lx() + self.m2_pitch > inst2.get_pin("data_{0}".format(loc)).rx()):
|
|
loc += 1
|
|
length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch
|
|
debug.check(loc<=self.num_wmasks,"Couldn't route the write mask select.")
|
|
else:
|
|
# Stride by the write size rather than finding the next pin to the right
|
|
loc += self.write_size
|
|
length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch
|
|
|
|
|
|
beg_pos = wmask_out_pin.center()
|
|
middle_pos = vector(length,wmask_out_pin.cy())
|
|
end_pos = vector(length, wdriver_en_pin.cy())
|
|
|
|
# Add via for the write driver array's enable input
|
|
self.add_via_center(layers=self.m1_stack,
|
|
offset=end_pos)
|
|
|
|
# Route between write mask AND array and write driver array
|
|
self.add_wire(self.m1_stack, [beg_pos, middle_pos, end_pos])
|
|
|
|
|
|
def route_column_mux_to_precharge_array(self, port):
|
|
""" Routing of BL and BR between col mux and precharge array """
|
|
|
|
# Only do this if we have a column mux!
|
|
if self.col_addr_size==0:
|
|
return
|
|
|
|
inst1 = self.column_mux_array_inst
|
|
inst2 = self.precharge_array_inst
|
|
if self.port==0:
|
|
self.connect_bitlines(inst1, inst2, self.num_cols, inst2_start_bit=1)
|
|
else:
|
|
self.connect_bitlines(inst1, inst2, self.num_cols)
|
|
|
|
|
|
def route_sense_amp_to_column_mux_or_precharge_array(self, port):
|
|
""" Routing of BL and BR between sense_amp and column mux or precharge array """
|
|
inst2 = self.sense_amp_array_inst
|
|
|
|
if self.col_addr_size>0:
|
|
# Sense amp is connected to the col mux
|
|
inst1 = self.column_mux_array_inst
|
|
inst1_bl_name = "bl_out_{}"
|
|
inst1_br_name = "br_out_{}"
|
|
start_bit = 0
|
|
else:
|
|
# Sense amp is directly connected to the precharge array
|
|
inst1 = self.precharge_array_inst
|
|
inst1_bl_name = "bl_{}"
|
|
inst1_br_name = "br_{}"
|
|
if self.port==0:
|
|
start_bit=1
|
|
else:
|
|
start_bit=0
|
|
|
|
|
|
self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
|
|
inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit)
|
|
|
|
|
|
def route_write_driver_to_column_mux_or_precharge_array(self, port):
|
|
""" Routing of BL and BR between sense_amp and column mux or precharge array """
|
|
inst2 = self.write_driver_array_inst
|
|
|
|
if self.col_addr_size>0:
|
|
# Write driver is connected to the col mux
|
|
inst1 = self.column_mux_array_inst
|
|
inst1_bl_name = "bl_out_{}"
|
|
inst1_br_name = "br_out_{}"
|
|
start_bit = 0
|
|
else:
|
|
# Sense amp is directly connected to the precharge array
|
|
inst1 = self.precharge_array_inst
|
|
inst1_bl_name = "bl_{}"
|
|
inst1_br_name = "br_{}"
|
|
if self.port==0:
|
|
start_bit=1
|
|
else:
|
|
start_bit=0
|
|
|
|
self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
|
|
inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit)
|
|
|
|
|
|
def route_write_driver_to_sense_amp(self, port):
|
|
""" Routing of BL and BR between write driver and sense amp """
|
|
|
|
inst1 = self.write_driver_array_inst
|
|
inst2 = self.sense_amp_array_inst
|
|
|
|
# These should be pitch matched in the cell library,
|
|
# but just in case, do a channel route.
|
|
self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size)
|
|
|
|
|
|
def route_bitline_pins(self):
|
|
""" Add the bitline pins for the given port """
|
|
|
|
# Connect one bitline to the RBL and offset the indices for the other BLs
|
|
if self.port==0:
|
|
self.copy_layout_pin(self.precharge_array_inst, "bl_0", "rbl_bl")
|
|
self.copy_layout_pin(self.precharge_array_inst, "br_0", "rbl_br")
|
|
bit_offset=1
|
|
elif self.port==1:
|
|
self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(self.num_cols), "rbl_bl")
|
|
self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(self.num_cols), "rbl_br")
|
|
bit_offset=0
|
|
else:
|
|
bit_offset=0
|
|
|
|
for bit in range(self.num_cols):
|
|
if self.precharge_array_inst:
|
|
self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(bit+bit_offset), "bl_{}".format(bit))
|
|
self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(bit+bit_offset), "br_{}".format(bit))
|
|
else:
|
|
debug.error("Didn't find precharge array.")
|
|
|
|
|
|
def route_control_pins(self):
|
|
""" Add the control pins: s_en, p_en_bar, w_en """
|
|
if self.precharge_array_inst:
|
|
self.copy_layout_pin(self.precharge_array_inst, "en_bar", "p_en_bar")
|
|
if self.column_mux_array_inst:
|
|
sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)]
|
|
for pin_name in sel_names:
|
|
self.copy_layout_pin(self.column_mux_array_inst, pin_name)
|
|
if self.sense_amp_array_inst:
|
|
self.copy_layout_pin(self.sense_amp_array_inst, "en", "s_en")
|
|
if self.write_driver_array_inst:
|
|
if self.write_mask_and_array_inst:
|
|
for bit in range(self.num_wmasks):
|
|
# Add write driver's en_{} pins
|
|
self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit))
|
|
else:
|
|
self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en")
|
|
if self.write_mask_and_array_inst:
|
|
self.copy_layout_pin(self.write_mask_and_array_inst, "en", "w_en")
|
|
|
|
|
|
|
|
def channel_route_bitlines(self, inst1, inst2, num_bits,
|
|
inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst1_start_bit=0,
|
|
inst2_bl_name="bl_{}", inst2_br_name="br_{}", inst2_start_bit=0):
|
|
"""
|
|
Route the bl and br of two modules using the channel router.
|
|
"""
|
|
|
|
# determine top and bottom automatically.
|
|
# since they don't overlap, we can just check the bottom y coordinate.
|
|
if inst1.by() < inst2.by():
|
|
(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
|
|
(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
|
|
else:
|
|
(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
|
|
(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
|
|
|
|
|
|
# Channel route each mux separately since we don't minimize the number
|
|
# of tracks in teh channel router yet. If we did, we could route all the bits at once!
|
|
offset = bottom_inst.ul() + vector(0,self.m1_pitch)
|
|
for bit in range(num_bits):
|
|
bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit+bottom_start_bit)), bottom_inst.get_pin(bottom_br_name.format(bit+bottom_start_bit))]
|
|
top_names = [top_inst.get_pin(top_bl_name.format(bit+top_start_bit)), top_inst.get_pin(top_br_name.format(bit+top_start_bit))]
|
|
route_map = list(zip(bottom_names, top_names))
|
|
self.create_horizontal_channel_route(route_map, offset, self.m1_stack)
|
|
|
|
|
|
def connect_bitlines(self, inst1, inst2, num_bits,
|
|
inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst1_start_bit=0,
|
|
inst2_bl_name="bl_{}", inst2_br_name="br_{}", inst2_start_bit=0):
|
|
|
|
"""
|
|
Connect the bl and br of two modules.
|
|
This assumes that they have sufficient space to create a jog
|
|
in the middle between the two modules (if needed).
|
|
"""
|
|
|
|
# determine top and bottom automatically.
|
|
# since they don't overlap, we can just check the bottom y coordinate.
|
|
if inst1.by() < inst2.by():
|
|
(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
|
|
(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
|
|
else:
|
|
(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
|
|
(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
|
|
|
|
for col in range(num_bits):
|
|
bottom_bl = bottom_inst.get_pin(bottom_bl_name.format(col+bottom_start_bit)).uc()
|
|
bottom_br = bottom_inst.get_pin(bottom_br_name.format(col+bottom_start_bit)).uc()
|
|
top_bl = top_inst.get_pin(top_bl_name.format(col+top_start_bit)).bc()
|
|
top_br = top_inst.get_pin(top_br_name.format(col+top_start_bit)).bc()
|
|
|
|
yoffset = 0.5*(top_bl.y+bottom_bl.y)
|
|
self.add_path("m2",[bottom_bl, vector(bottom_bl.x,yoffset),
|
|
vector(top_bl.x,yoffset), top_bl])
|
|
self.add_path("m2",[bottom_br, vector(bottom_br.x,yoffset),
|
|
vector(top_br.x,yoffset), top_br])
|
|
|
|
def graph_exclude_precharge(self):
|
|
"""Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
|
|
if self.precharge_array_inst:
|
|
self.graph_inst_exclude.add(self.precharge_array_inst)
|
|
|