mirror of https://github.com/VLSIDA/OpenRAM.git
30 lines
835 B
Python
30 lines
835 B
Python
import globals
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import design
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from math import log
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import design
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from tech import GDS,layer
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import utils
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class dff(design.design):
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"""
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Memory address flip-flop
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"""
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pin_names = ["D", "Q", "clk", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"])
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def __init__(self, name="dff"):
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design.design.__init__(self, name)
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self.width = dff.width
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self.height = dff.height
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self.pin_map = dff.pin_map
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def analytical_delay(self, slew, load = 0.0):
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# dont know how to calculate this now, use constant in tech file
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from tech import spice
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result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
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return result
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