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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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abb9af0ea8a05b3be3280da38292f6eb9c21c47d
OpenRAM/compiler/characterizer
T
History
jsowash a6bb410560 Begin implementing a write mask layout as the port data level.
2019-08-07 09:12:21 -07:00
..
__init__.py
Removed unused characterization module.
2019-07-30 20:33:17 -07:00
bit_polarity.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
charutils.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
delay.py
Added graph fixes to handmade multiport cells.
2019-07-30 20:31:32 -07:00
functional.py
Begin implementing a write mask layout as the port data level.
2019-08-07 09:12:21 -07:00
lib.py
Reapply jsowash update without spice model file
2019-06-24 08:59:58 -07:00
logical_effort.py
Fix space before comment
2019-06-14 08:43:41 -07:00
measurements.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
model_check.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
setup_hold.py
Fix space before comment
2019-06-14 08:43:41 -07:00
simulation.py
Removed comments for rw pen() and added a wmask func test.
2019-07-25 12:24:27 -07:00
sram_op.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
stimuli.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
trim_spice.py
Fix space before comment
2019-06-14 08:43:41 -07:00
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