mirror of https://github.com/VLSIDA/OpenRAM.git
49 lines
1.5 KiB
Python
49 lines
1.5 KiB
Python
import globals
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import design
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from math import log
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import design
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from tech import GDS,layer
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import utils
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class dff(design.design):
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"""
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Memory address flip-flop
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"""
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pin_names = ["D", "Q", "clk", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"])
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def __init__(self, name="dff"):
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design.design.__init__(self, name)
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self.width = dff.width
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self.height = dff.height
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self.pin_map = dff.pin_map
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def analytical_power(self, proc, vdd, temp, load):
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"""Returns dynamic and leakage power. Results in nW"""
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from tech import spice
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["msflop_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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from tech import spice, parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transition_prob = spice["flop_transition_prob"]
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return transition_prob*(c_load + c_para)
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def analytical_delay(self, slew, load = 0.0):
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# dont know how to calculate this now, use constant in tech file
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from tech import spice
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result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
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return result
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