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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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OpenRAM/compiler/base
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Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
..
contact.py
Remove unique id in contact that was used for debugging
2018-09-04 16:40:52 -07:00
design.py
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
geometry.py
Add back LEF blockages. Remove "absolute" flags from GDS output
2018-09-05 09:28:43 -07:00
hierarchy_design.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
hierarchy_layout.py
Comment debug for possible performance issue
2018-09-24 11:44:32 -07:00
hierarchy_spice.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
lef.py
…
path.py
…
pin_layout.py
Add inflate blockages and remove pins from blockages.
2018-09-05 11:06:17 -07:00
route.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
utils.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
vector.py
…
verilog.py
…
wire.py
…
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