mirror of https://github.com/VLSIDA/OpenRAM.git
17 lines
616 B
Tcl
17 lines
616 B
Tcl
# Setup file for netgen
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ignore class c
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equate class {-circuit1 nfet} {-circuit2 n}
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equate class {-circuit1 pfet} {-circuit2 p}
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# We must flatten these because the ports are disconnected
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flatten class {-circuit1 dummy_cell_6t}
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flatten class {-circuit1 dummy_cell_1rw_1r}
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flatten class {-circuit1 dummy_cell_1w_1r}
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flatten class {-circuit1 pbitcell}
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flatten class {-circuit1 pbitcell_0}
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flatten class {-circuit1 pbitcell_1}
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property {-circuit1 nfet} remove as ad ps pd
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property {-circuit1 pfet} remove as ad ps pd
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property {-circuit2 n} remove as ad ps pd
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property {-circuit2 p} remove as ad ps pd
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permute transistors
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