mirror of https://github.com/VLSIDA/OpenRAM.git
62 lines
2.0 KiB
Python
Executable File
62 lines
2.0 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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import debug
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class multibank_verilog_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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globals.init_openram(config_file)
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OPTS.route_supplies=False
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OPTS.check_lvsdrc=False
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OPTS.netlist_only=True
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from modules import sram
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from modules import sram_config
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c = sram_config(word_size=2,
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num_words=16,
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num_banks=2)
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c.words_per_row=1
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c.recompute_sizes()
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debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 2 bank")
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# This doesn't have to use the factory since worst case
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# it will just replaece the top-level module of the same name
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s = sram(c, "sram_2_16_2_{0}".format(OPTS.tech_name))
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vfile = s.name + ".v"
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vname = OPTS.openram_temp + vfile
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v1bfile = s.name + "_1bank.v"
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v1bname = OPTS.openram_temp + v1bfile
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s.verilog_write(vname)
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# let's diff the result with a golden model
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multi_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile)
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self.assertTrue(self.isdiff(vname, multi_golden))
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one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bfile)
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self.assertTrue(self.isdiff(v1bname, one_golden))
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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