mirror of https://github.com/VLSIDA/OpenRAM.git
129 lines
4.2 KiB
Python
129 lines
4.2 KiB
Python
import debug
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from tech import drc
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from math import log
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from vector import vector
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from globals import OPTS
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from pnand2 import pnand2
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from pinv import pinv
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import pgate
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class pand2(pgate.pgate):
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"""
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This is a simple buffer used for driving loads.
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"""
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from importlib import reload
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c = reload(__import__(OPTS.bitcell))
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bitcell = getattr(c, OPTS.bitcell)
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unique_id = 1
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def __init__(self, size=1, height=None, name=""):
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self.size = size
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if name=="":
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name = "pand2_{0}_{1}".format(size, pand2.unique_id)
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pand2.unique_id += 1
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pgate.pgate.__init__(self, name, height)
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debug.info(1, "Creating {}".format(self.name))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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self.nand = pnand2(height=self.height)
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self.add_mod(self.nand)
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self.inv = pinv(size=self.size, height=self.height)
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self.add_mod(self.inv)
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def create_layout(self):
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self.width = self.nand.width + self.inv.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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def add_pins(self):
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self.add_pin("A")
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self.add_pin("B")
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self.add_pin("Z")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_insts(self):
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self.nand_inst=self.add_inst(name="pand2_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"])
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self.inv_inst=self.add_inst(name="pand2_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0,0))
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(),0))
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def add_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.inv_inst.get_pin("A")
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mid1_point = vector(0.5*(z1_pin.cx()+a2_pin.cx()), z1_pin.cy())
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mid2_point = vector(mid1_point, a2_pin.cy())
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self.add_path("metal1", [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()])
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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vdd_pin=self.inv_inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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# Continous gnd rail along with label.
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gnd_pin=self.inv_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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pin = self.inv_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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for pin_name in ["A","B"]:
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pin = self.nand_inst.get_pin(pin_name)
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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def analytical_delay(self, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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nand_delay = selfnand.analytical_delay(slew=slew, load=self.inv.input_load())
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inv_delay = self.inv.analytical_delay(slew=nand_delay.slew, load=load)
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return nand_delay + inv_delay
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