mirror of https://github.com/VLSIDA/OpenRAM.git
20 lines
430 B
Python
20 lines
430 B
Python
word_size = 64
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num_words = 128
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tech_name = "scn4m_subm"
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process_corners = ["TT"]
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supply_voltages = [5.0]
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temperatures = [25]
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route_supplies = True
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check_lvsdrc = True
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output_path = "/home/jesse/thesis/outputs/run5"
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output_name = "sram_{0}_{1}_{2}".format(word_size,
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num_words,
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tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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