mirror of https://github.com/VLSIDA/OpenRAM.git
14 lines
341 B
Python
14 lines
341 B
Python
from verilog_template import verilog_template
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t = verilog_template('../sram/multibank_template.v')
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t.readTemplate()
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t.setSectionRepeat('RW_PORTS', 1)
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t.setSectionRepeat('R_PORTS', 0)
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t.setSectionRepeat('BANK_DEFS', 2)
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t.setSectionRepeat('BANK_INIT', 2)
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t.setSectionRepeat('BANK_CASE', 2)
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t.setTextDict('PORT_NUM', 0)
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t.generate('test.v')
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