mirror of https://github.com/VLSIDA/OpenRAM.git
200 lines
9.2 KiB
Python
200 lines
9.2 KiB
Python
import sys,re,shutil
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from design import design
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import debug
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import math
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import tech
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import random
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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class simulation():
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def __init__(self, sram, spfile, corner):
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self.sram = sram
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self.name = self.sram.name
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self.word_size = self.sram.word_size
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self.addr_size = self.sram.addr_size
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self.num_cols = self.sram.num_cols
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self.num_rows = self.sram.num_rows
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self.num_banks = self.sram.num_banks
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self.sp_file = spfile
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self.total_ports = self.sram.total_ports
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self.total_write = self.sram.total_write
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self.total_read = self.sram.total_read
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self.read_index = self.sram.read_index
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self.write_index = self.sram.write_index
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self.num_rw_ports = self.sram.num_rw_ports
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self.port_id = self.sram.port_id
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def set_corner(self,corner):
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""" Set the corner values """
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self.corner = corner
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(self.process, self.vdd_voltage, self.temperature) = corner
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def set_spice_constants(self):
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""" sets feasible timing parameters """
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self.period = tech.spice["feasible_period"]
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self.slew = tech.spice["rise_time"]*2
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self.load = tech.spice["msflop_in_cap"]*4
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self.gnd_voltage = 0
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def set_stimulus_variables(self):
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# Clock signals
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self.cycle_times = []
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self.t_current = 0
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# control signals: only one cs_b for entire multiported sram, one we_b for each write port
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self.csb_values = [[] for port in range(self.total_ports)]
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self.web_values = [[] for port in range(self.num_rw_ports)]
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# Three dimensional list to handle each addr and data bits for wach port over the number of checks
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self.addr_values = [[[] for bit in range(self.addr_size)] for port in range(self.total_ports)]
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self.data_values = [[[] for bit in range(self.word_size)] for port in range(self.total_write)]
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# For generating comments in SPICE stimulus
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self.cycle_comments = []
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def add_control_one_port(self, port, op):
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"""Appends control signals for operation to a given port"""
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#Determine values to write to port
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web_val = 1
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csb_val = 1
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if op == "read":
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csb_val = 0
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elif op == "write":
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csb_val = 0
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web_val = 0
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elif op != "noop":
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debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port,op),1)
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# Append the values depending on the type of port
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self.csb_values[port].append(csb_val)
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# If port is in both lists, add rw control signal. Condition indicates its a RW port.
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if port < self.num_rw_ports:
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self.web_values[port].append(web_val)
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def add_data(self, data, port):
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""" Add the array of data values """
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debug.check(len(data)==self.word_size, "Invalid data word size.")
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#debug.check(port < len(self.data_values), "Port number cannot index data values.")
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bit = self.word_size - 1
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for c in data:
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if c=="0":
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self.data_values[port][bit].append(0)
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elif c=="1":
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self.data_values[port][bit].append(1)
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else:
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debug.error("Non-binary data string",1)
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bit -= 1
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def add_address(self, address, port):
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""" Add the array of address values """
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debug.check(len(address)==self.addr_size, "Invalid address size.")
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bit = self.addr_size - 1
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for c in address:
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if c=="0":
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self.addr_values[port][bit].append(0)
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elif c=="1":
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self.addr_values[port][bit].append(1)
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else:
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debug.error("Non-binary address string",1)
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bit -= 1
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def add_write(self, comment, address, data, port):
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""" Add the control values for a write cycle. """
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debug.info(1, comment)
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debug.check(port in self.write_index, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_index))
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self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
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self.t_current,
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comment,
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port))
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "write")
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self.add_data(data,port)
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self.add_address(address,port)
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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for unselected_port in range(self.total_ports):
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if unselected_port != port:
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self.add_noop_one_port(address, noop_data, unselected_port)
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def add_read(self, comment, address, data, port):
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""" Add the control values for a read cycle. """
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debug.info(1, comment)
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debug.check(port in self.read_index, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_index))
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self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
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self.t_current,
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comment,
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port))
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "read")
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#If the port is also a readwrite then add data.
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if port in self.write_index:
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self.add_data(data,port)
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self.add_address(address, port)
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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for unselected_port in range(self.total_ports):
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if unselected_port != port:
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self.add_noop_one_port(address, noop_data, unselected_port)
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def add_noop_all_ports(self, comment, address, data):
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""" Add the control values for a noop to all ports. """
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debug.info(1, comment)
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self.cycle_comments.append("Cycle {0:2d}\tPort All\t{1:5.2f}ns:\t{2}".format(len(self.cycle_times),
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self.t_current,
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comment))
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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for port in range(self.total_ports):
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self.add_noop_one_port(address, data, port)
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def add_write_one_port(self, comment, address, data, port):
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""" Add the control values for a write cycle. Does not increment the period. """
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debug.check(port in self.write_index, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_index))
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debug.info(1, comment)
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self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
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self.t_current,
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comment,
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port))
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self.add_control_one_port(port, "write")
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self.add_data(data,port)
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self.add_address(address,port)
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def add_read_one_port(self, comment, address, data, port):
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""" Add the control values for a read cycle. Does not increment the period. """
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debug.check(port in self.read_index, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_index))
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debug.info(1, comment)
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self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
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self.t_current,
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comment,
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port))
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self.add_control_one_port(port, "read")
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#If the port is also a readwrite then add data.
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if port in self.write_index:
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self.add_data(data,port)
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self.add_address(address, port)
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def add_noop_one_port(self, address, data, port):
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""" Add the control values for a noop to a single port. Does not increment the period. """
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self.add_control_one_port(port, "noop")
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if port in self.write_index:
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self.add_data(data,port)
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self.add_address(address, port)
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