mirror of https://github.com/VLSIDA/OpenRAM.git
69 lines
3.6 KiB
TeX
69 lines
3.6 KiB
TeX
\section{Introduction}
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\label{sec:introduction}
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% why memory compilers are important
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Static Random Access Memories (SRAMs) have become a standard component
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embedded in all System-on-Chip (SoC), Application-Specific Integrated
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Circuit (ASIC), and micro-processor designs. Their wide application
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leads to a variety of requirements in circuit design and memory
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configuration. However, manual design is
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too time consuming. The
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regular structure of memories leads well to automation that produces
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size and configuration variations quickly, but developing this with
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multiple technologies and tool methodologies is challenging. In
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addition, memory designs play a significant role in overall system
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performance and costs, so optimization is important. Thus, a memory
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compiler is a critical tool.
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% why academics need memory compilers
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Most academic ICs design methodologies are limited by the availability
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of memories. Many standard-cell Process Design Kits (PDKs) are
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available from foundries and vendors, but these PDKs frequently do not
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come with memory arrays or memory compilers. If a memory compiler is
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freely available, it often only supports a generic process technology
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that is not fabricable. Due to academic funding restrictions,
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commercial industry solutions are often not feasible for
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researchers. In addition, these commercial solutions are limited in
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customization of the memory sizes and specific components of the
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memory. PDKs may have the options to request \enquote{black box}
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memory models, but these are also not modifiable and have limited
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available configurations. These restrictions and licensing issues make
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comparison and experimentation with real world memories impossible.
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% manually designing is time consuming
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Academic researchers are able to design their own custom memories, but
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this can be a tedious and time-consuming task and may not be the intended
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purpose of the research. Frequently, the memory design is the bare
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minimum that the research project requires,
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and, because of this, the memory designs are often inferior and are not
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optimized. In memory research, peripheral circuits are often not
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considered when comparing memory performance and density. The
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lack of a customizable compiler makes it difficult for researchers to
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prototype and verify circuits and methodologies beyond a single row or
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column of memory cells.
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% what are the goals of OpenRAM
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The OpenRAM project aims to provide an open-source memory compiler
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development framework for memories. It provides reference circuit and
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physical implementations in a generic $45$nm technology and fabricable
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Scalable CMOS (SCMOS), but it has also been ported to several
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commercial technology nodes using a simple technology file. OpenRAM
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also includes a characterization methodology so that it can generate
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the timing and power characterization results in addition to circuits and
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layout while remaining independent of specific commercial tools. Most
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importantly, OpenRAM is completely user-modifiable since all source
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code is open source at:
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\begin{center}
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\url{https://openram.soe.ucsc.edu/}
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\end{center}
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The remainder of this paper is organized as follows:
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Section~\ref{sec:background} provides a background on previous memory
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compilers. Section~\ref{sec:architecture} presents the reference
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memory architecture in OpenRAM. Section~\ref{sec:implementation}
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specifically introduces the implementation and main features of the
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OpenRAM memory compiler. In Section~\ref{sec:results}, an analysis of
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the area, timing and power is shown for different sizes and
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technologies of memory. Finally, the paper is summarized in
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Section~\ref{sec:conclusions}.
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