mirror of https://github.com/VLSIDA/OpenRAM.git
42 lines
1.6 KiB
Python
42 lines
1.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import utils
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from tech import GDS,layer
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class write_driver(design.design):
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"""
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Tristate write driver to be active during write operations only.
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This module implements the write driver cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library.
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"""
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pin_names = ["din", "bl", "br", "en", "vdd", "gnd"]
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type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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(width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
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def __init__(self, name):
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design.design.__init__(self, name)
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debug.info(2, "Create write_driver")
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self.width = write_driver.width
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self.height = write_driver.height
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self.pin_map = write_driver.pin_map
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self.add_pin_types(self.type_list)
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def get_w_en_cin(self):
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"""Get the relative capacitance of a single input"""
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# This is approximated from SCMOS. It has roughly 5 3x transistor gates.
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return 5*3
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets) |