mirror of https://github.com/VLSIDA/OpenRAM.git
876 lines
40 KiB
Python
876 lines
40 KiB
Python
import sys,re,shutil
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import debug
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import tech
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import math
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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class delay():
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"""Functions to measure the delay and power of an SRAM at a given address and
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data bit.
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In general, this will perform the following actions:
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1) Trim the netlist to remove unnecessary logic.
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2) Find a feasible clock period using max load/slew on the trimmed netlist.
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3) Characterize all loads/slews and consider fail when delay is greater than 5% of feasible delay using trimmed netlist.
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4) Measure the leakage during the last cycle of the trimmed netlist when there is no operation.
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5) Measure the leakage of the whole netlist (untrimmed) in each corner.
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6) Subtract the trimmed leakage and add the untrimmed leakage to the power.
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Netlist trimming can be removed by setting OPTS.trim_netlist to
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False, but this is VERY slow.
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"""
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def __init__(self, sram, spfile, corner):
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self.sram = sram
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self.name = sram.name
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self.word_size = self.sram.word_size
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self.addr_size = self.sram.addr_size
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self.num_cols = self.sram.num_cols
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self.num_rows = self.sram.num_rows
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self.num_banks = self.sram.num_banks
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self.sp_file = spfile
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# These are the member variables for a simulation
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self.period = 0
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self.set_load_slew(0,0)
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self.set_corner(corner)
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def set_corner(self,corner):
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""" Set the corner values """
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self.corner = corner
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(self.process, self.vdd_voltage, self.temperature) = corner
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def set_load_slew(self,load,slew):
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""" Set the load and slew """
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self.load = load
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self.slew = slew
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def check_arguments(self):
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"""Checks if arguments given for write_stimulus() meets requirements"""
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try:
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int(self.probe_address, 2)
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except ValueError:
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debug.error("Probe Address is not of binary form: {0}".format(self.probe_address),1)
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if len(self.probe_address) != self.addr_size:
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debug.error("Probe Address's number of bits does not correspond to given SRAM",1)
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if not isinstance(self.probe_data, int) or self.probe_data>self.word_size or self.probe_data<0:
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debug.error("Given probe_data is not an integer to specify a data bit",1)
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def write_generic_stimulus(self):
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""" Create the instance, supplies, loads, and access transistors. """
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# add vdd/gnd statements
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self.sf.write("\n* Global Power Supplies\n")
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self.stim.write_supply()
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# instantiate the sram
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_sram(abits=self.addr_size,
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dbits=self.word_size,
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sram_name=self.name)
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self.sf.write("\n* SRAM output loads\n")
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for readwrite_output in range(OPTS.rw_ports):
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for i in range(self.word_size):
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self.sf.write("CD_RWP{0}{1} DOUT_RWP{0}[{1}] 0 {2}f\n".format(readwrite_output,i,self.load))
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for read_port in range(OPTS.r_ports):
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for i in range(self.word_size):
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self.sf.write("CD_RP{0}{1} DOUT_RP{0}[{1}] 0 {2}f\n".format(read_port,i,self.load))
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def write_delay_stimulus(self):
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""" Creates a stimulus file for simulations to probe a bitcell at a given clock period.
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Address and bit were previously set with set_probe().
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Input slew (in ns) and output capacitive load (in fF) are required for charaterization.
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"""
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self.check_arguments()
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# obtains list of time-points for each rising clk edge
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self.create_test_cycles()
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# creates and opens stimulus file for writing
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Delay stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(self.period,
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self.load,
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self.slew))
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self.stim = stimuli(self.sf, self.corner)
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# include files in stimulus file
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self.stim.write_include(self.trim_sp_file)
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self.write_generic_stimulus()
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# generate data and addr signals
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self.sf.write("\n* Generation of data and address signals\n")
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self.gen_data()
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self.gen_addr()
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# generate control signals
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self.sf.write("\n* Generation of control signals\n")
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self.gen_control()
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self.sf.write("\n* Generation of global clock signal\n")
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self.stim.gen_pulse(sig_name="CLK",
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v1=0,
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v2=self.vdd_voltage,
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offset=self.period,
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period=self.period,
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t_rise=self.slew,
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t_fall=self.slew)
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self.write_delay_measures()
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# run until the end of the cycle time
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self.stim.write_control(self.cycle_times[-1] + self.period)
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self.sf.close()
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def write_power_stimulus(self, trim):
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""" Creates a stimulus file to measure leakage power only.
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This works on the *untrimmed netlist*.
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"""
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self.check_arguments()
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# obtains list of time-points for each rising clk edge
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self.create_test_cycles()
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# creates and opens stimulus file for writing
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Power stimulus for period of {0}n\n\n".format(self.period))
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self.stim = stimuli(self.sf, self.corner)
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# include UNTRIMMED files in stimulus file
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if trim:
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self.stim.write_include(self.trim_sp_file)
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else:
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self.stim.write_include(self.sim_sp_file)
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self.write_generic_stimulus()
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# generate data and addr signals
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self.sf.write("\n* Generation of data and address signals\n")
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for readwrite_input in range(OPTS.rw_ports):
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for i in range(self.word_size):
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self.stim.gen_constant(sig_name="DIN_RWP{0}[{1}] ".format(readwrite_input, i),
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v_val=0)
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for write_port in range(OPTS.w_ports):
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for i in range(self.word_size):
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self.stim.gen_constant(sig_name="DIN_WP{0}[{1}] ".format(write_port, i),
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v_val=0)
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for i in range(self.addr_size):
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self.stim.gen_constant(sig_name="A[{0}]".format(i),
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v_val=0)
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for readwrite_addr in range(OPTS.rw_ports):
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for i in range(self.addr_size):
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self.stim.gen_constant(sig_name="A_RWP{0}[{1}]".format(readwrite_addr,i),
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v_val=0)
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for write_addr in range(OPTS.w_ports):
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for i in range(self.addr_size):
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self.stim.gen_constant(sig_name="A_WP{0}[{1}]".format(write_addr,i),
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v_val=0)
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for read_addr in range(OPTS.r_ports):
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for i in range(self.addr_size):
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self.stim.gen_constant(sig_name="A_RP{0}[{1}]".format(read_addr,i),
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v_val=0)
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# generate control signals
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self.sf.write("\n* Generation of control signals\n")
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self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage)
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self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage)
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self.sf.write("\n* Generation of global clock signal\n")
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self.stim.gen_constant(sig_name="CLK", v_val=0)
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self.write_power_measures()
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# run until the end of the cycle time
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self.stim.write_control(2*self.period)
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self.sf.close()
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def write_delay_measures(self):
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"""
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Write the measure statements to quantify the delay and power results.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and
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# what is happening
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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# Trigger on the clk of the appropriate cycle
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trig_name = "clk"
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targ_port = 0
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#Target name should be an input to the function or a member variable. That way, the ports can be singled out for testing
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targ_name = "{0}".format("DOUT_RWP{0}[{1}]".format(targ_port,self.probe_data))
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trig_val = targ_val = 0.5 * self.vdd_voltage
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# Delay the target to measure after the negative edge
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self.stim.gen_meas_delay(meas_name="DELAY_HL",
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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targ_val=targ_val,
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trig_dir="RISE",
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targ_dir="FALL",
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle])
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self.stim.gen_meas_delay(meas_name="DELAY_LH",
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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targ_val=targ_val,
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trig_dir="RISE",
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targ_dir="RISE",
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trig_td=self.cycle_times[self.read1_cycle],
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targ_td=self.cycle_times[self.read1_cycle])
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self.stim.gen_meas_delay(meas_name="SLEW_HL",
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trig_name=targ_name,
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targ_name=targ_name,
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trig_val=0.9*self.vdd_voltage,
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targ_val=0.1*self.vdd_voltage,
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trig_dir="FALL",
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targ_dir="FALL",
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trig_td=self.cycle_times[self.read0_cycle],
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targ_td=self.cycle_times[self.read0_cycle])
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self.stim.gen_meas_delay(meas_name="SLEW_LH",
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trig_name=targ_name,
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targ_name=targ_name,
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trig_val=0.1*self.vdd_voltage,
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targ_val=0.9*self.vdd_voltage,
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trig_dir="RISE",
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targ_dir="RISE",
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trig_td=self.cycle_times[self.read1_cycle],
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targ_td=self.cycle_times[self.read1_cycle])
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# add measure statements for power
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t_initial = self.cycle_times[self.write0_cycle]
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t_final = self.cycle_times[self.write0_cycle+1]
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self.stim.gen_meas_power(meas_name="WRITE0_POWER",
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.write1_cycle]
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t_final = self.cycle_times[self.write1_cycle+1]
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self.stim.gen_meas_power(meas_name="WRITE1_POWER",
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.read0_cycle]
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t_final = self.cycle_times[self.read0_cycle+1]
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self.stim.gen_meas_power(meas_name="READ0_POWER",
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t_initial=t_initial,
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t_final=t_final)
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t_initial = self.cycle_times[self.read1_cycle]
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t_final = self.cycle_times[self.read1_cycle+1]
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self.stim.gen_meas_power(meas_name="READ1_POWER",
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t_initial=t_initial,
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t_final=t_final)
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def write_power_measures(self):
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"""
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Write the measure statements to quantify the leakage power only.
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"""
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self.sf.write("\n* Measure statements for idle leakage power\n")
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# add measure statements for power
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t_initial = self.period
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t_final = 2*self.period
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self.stim.gen_meas_power(meas_name="leakage_power",
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t_initial=t_initial,
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t_final=t_final)
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def find_feasible_period(self):
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"""
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Uses an initial period and finds a feasible period before we
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run the binary search algorithm to find min period. We check if
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the given clock period is valid and if it's not, we continue to
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double the period until we find a valid period to use as a
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starting point.
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"""
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feasible_period = float(tech.spice["feasible_period"])
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#feasible_period = float(2.5)#What happens if feasible starting point is wrong?
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time_out = 8
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while True:
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debug.info(1, "Trying feasible period: {0}ns".format(feasible_period))
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time_out -= 1
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if (time_out <= 0):
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debug.error("Timed out, could not find a feasible period.",2)
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self.period = feasible_period
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(success, results)=self.run_delay_simulation()
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if not success:
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feasible_period = 2 * feasible_period
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continue
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feasible_delay_lh = results["delay_lh"]
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feasible_slew_lh = results["slew_lh"]
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feasible_delay_hl = results["delay_hl"]
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feasible_slew_hl = results["slew_hl"]
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delay_str = "feasible_delay {0:.4f}ns/{1:.4f}ns".format(feasible_delay_lh, feasible_delay_hl)
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slew_str = "slew {0:.4f}ns/{1:.4f}ns".format(feasible_slew_lh, feasible_slew_hl)
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debug.info(1, "Found feasible_period: {0}ns {1} {2} ".format(feasible_period,
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delay_str,
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slew_str))
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self.period = feasible_period
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return (feasible_delay_lh, feasible_delay_hl)
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def run_delay_simulation(self):
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"""
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This tries to simulate a period and checks if the result works. If
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so, it returns True and the delays, slews, and powers. It
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works on the trimmed netlist by default, so powers do not
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include leakage of all cells.
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"""
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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self.stim.run_sim()
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delay_hl = parse_spice_list("timing", "delay_hl")
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delay_lh = parse_spice_list("timing", "delay_lh")
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slew_hl = parse_spice_list("timing", "slew_hl")
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slew_lh = parse_spice_list("timing", "slew_lh")
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delays = (delay_hl, delay_lh, slew_hl, slew_lh)
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read0_power=parse_spice_list("timing", "read0_power")
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write0_power=parse_spice_list("timing", "write0_power")
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read1_power=parse_spice_list("timing", "read1_power")
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write1_power=parse_spice_list("timing", "write1_power")
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if not self.check_valid_delays(delays):
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return (False,{})
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# For debug, you sometimes want to inspect each simulation.
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#key=raw_input("press return to continue")
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# Scale results to ns and mw, respectively
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result = { "delay_hl" : delay_hl*1e9,
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"delay_lh" : delay_lh*1e9,
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"slew_hl" : slew_hl*1e9,
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"slew_lh" : slew_lh*1e9,
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"read0_power" : read0_power*1e3,
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"read1_power" : read1_power*1e3,
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"write0_power" : write0_power*1e3,
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"write1_power" : write1_power*1e3}
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# The delay is from the negative edge for our SRAM
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return (True,result)
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def run_power_simulation(self):
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"""
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This simulates a disabled SRAM to get the leakage power when it is off.
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"""
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self.write_power_stimulus(trim=False)
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self.stim.run_sim()
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leakage_power=parse_spice_list("timing", "leakage_power")
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debug.check(leakage_power!="Failed","Could not measure leakage power.")
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self.write_power_stimulus(trim=True)
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self.stim.run_sim()
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trim_leakage_power=parse_spice_list("timing", "leakage_power")
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debug.check(trim_leakage_power!="Failed","Could not measure leakage power.")
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# For debug, you sometimes want to inspect each simulation.
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#key=raw_input("press return to continue")
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return (leakage_power*1e3, trim_leakage_power*1e3)
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def check_valid_delays(self, delay_tuple):
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""" Check if the measurements are defined and if they are valid. """
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(delay_hl, delay_lh, slew_hl, slew_lh) = delay_tuple
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period_load_slew_str = "period {0} load {1} slew {2}".format(self.period,self.load, self.slew)
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# if it failed or the read was longer than a period
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if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
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delays_str = "delay_hl={0} delay_lh={1}".format(delay_hl, delay_lh)
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slews_str = "slew_hl={0} slew_lh={1}".format(slew_hl,slew_lh)
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debug.info(2,"Failed simulation (in sec):\n\t\t{0}\n\t\t{1}\n\t\t{2}".format(period_load_slew_str,
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delays_str,
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slews_str))
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return False
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# Scale delays to ns (they previously could have not been floats)
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delay_hl *= 1e9
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delay_lh *= 1e9
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slew_hl *= 1e9
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slew_lh *= 1e9
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delays_str = "delay_hl={0} delay_lh={1}".format(delay_hl, delay_lh)
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slews_str = "slew_hl={0} slew_lh={1}".format(slew_hl,slew_lh)
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if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period:
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debug.info(2,"UNsuccessful simulation (in ns):\n\t\t{0}\n\t\t{1}\n\t\t{2}".format(period_load_slew_str,
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delays_str,
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slews_str))
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return False
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else:
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debug.info(2,"Successful simulation (in ns):\n\t\t{0}\n\t\t{1}\n\t\t{2}".format(period_load_slew_str,
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delays_str,
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slews_str))
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return True
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def find_min_period(self, feasible_delay_lh, feasible_delay_hl):
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"""
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Searches for the smallest period with output delays being within 5% of
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long period.
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"""
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previous_period = ub_period = self.period
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lb_period = 0.0
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# Binary search algorithm to find the min period (max frequency) of design
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time_out = 25
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while True:
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time_out -= 1
|
|
if (time_out <= 0):
|
|
debug.error("Timed out, could not converge on minimum period.",2)
|
|
|
|
target_period = 0.5 * (ub_period + lb_period)
|
|
self.period = target_period
|
|
debug.info(1, "MinPeriod Search: {0}ns (ub: {1} lb: {2})".format(target_period,
|
|
ub_period,
|
|
lb_period))
|
|
|
|
if self.try_period(feasible_delay_lh, feasible_delay_hl):
|
|
ub_period = target_period
|
|
else:
|
|
lb_period = target_period
|
|
#debug.error("Lower bound "+str(target_period)+" caused a failed simulation.Exiting...",2)
|
|
|
|
if relative_compare(ub_period, lb_period, error_tolerance=0.05):
|
|
# ub_period is always feasible
|
|
return ub_period
|
|
|
|
|
|
def try_period(self, feasible_delay_lh, feasible_delay_hl):
|
|
"""
|
|
This tries to simulate a period and checks if the result
|
|
works. If it does and the delay is within 5% still, it returns True.
|
|
"""
|
|
|
|
# Checking from not data_value to data_value
|
|
self.write_delay_stimulus()
|
|
self.stim.run_sim()
|
|
delay_hl = parse_spice_list("timing", "delay_hl")
|
|
delay_lh = parse_spice_list("timing", "delay_lh")
|
|
slew_hl = parse_spice_list("timing", "slew_hl")
|
|
slew_lh = parse_spice_list("timing", "slew_lh")
|
|
# if it failed or the read was longer than a period
|
|
if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float:
|
|
debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
|
|
delay_hl,
|
|
delay_lh,
|
|
slew_hl,
|
|
slew_lh))
|
|
return False
|
|
delay_hl *= 1e9
|
|
delay_lh *= 1e9
|
|
slew_hl *= 1e9
|
|
slew_lh *= 1e9
|
|
if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period:
|
|
debug.info(2,"Too long delay/slew: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
|
|
delay_hl,
|
|
delay_lh,
|
|
slew_hl,
|
|
slew_lh))
|
|
return False
|
|
else:
|
|
if not relative_compare(delay_lh,feasible_delay_lh,error_tolerance=0.05):
|
|
debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delay_lh))
|
|
return False
|
|
elif not relative_compare(delay_hl,feasible_delay_hl,error_tolerance=0.05):
|
|
debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delay_hl))
|
|
return False
|
|
|
|
|
|
#key=raw_input("press return to continue")
|
|
|
|
debug.info(2,"Successful period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period,
|
|
delay_hl,
|
|
delay_lh,
|
|
slew_hl,
|
|
slew_lh))
|
|
return True
|
|
|
|
def set_probe(self,probe_address, probe_data):
|
|
""" Probe address and data can be set separately to utilize other
|
|
functions in this characterizer besides analyze."""
|
|
self.probe_address = probe_address
|
|
self.probe_data = probe_data
|
|
|
|
self.prepare_netlist()
|
|
|
|
|
|
def prepare_netlist(self):
|
|
""" Prepare a trimmed netlist and regular netlist. """
|
|
|
|
# Set up to trim the netlist here if that is enabled
|
|
if OPTS.trim_netlist:
|
|
self.trim_sp_file = "{}reduced.sp".format(OPTS.openram_temp)
|
|
self.trimsp=trim_spice(self.sp_file, self.trim_sp_file)
|
|
self.trimsp.set_configuration(self.num_banks,
|
|
self.num_rows,
|
|
self.num_cols,
|
|
self.word_size)
|
|
self.trimsp.trim(self.probe_address,self.probe_data)
|
|
else:
|
|
# The non-reduced netlist file when it is disabled
|
|
self.trim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
|
|
|
|
# The non-reduced netlist file for power simulation
|
|
self.sim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
|
|
# Make a copy in temp for debugging
|
|
shutil.copy(self.sp_file, self.sim_sp_file)
|
|
|
|
|
|
|
|
def analyze(self,probe_address, probe_data, slews, loads):
|
|
"""
|
|
Main function to characterize an SRAM for a table. Computes both delay and power characterization.
|
|
"""
|
|
# Data structure for all the characterization values
|
|
char_data = {}
|
|
|
|
self.set_probe(probe_address, probe_data)
|
|
|
|
#A helper functions to set port names for the characterizer.
|
|
self.gen_port_names()
|
|
|
|
# This is for debugging a full simulation
|
|
# debug.info(0,"Debug simulation running...")
|
|
# target_period=50.0
|
|
# feasible_delay_lh=0.059083183
|
|
# feasible_delay_hl=0.17953789
|
|
# load=1.6728
|
|
# slew=0.04
|
|
# self.try_period(target_period, feasible_delay_lh, feasible_delay_hl)
|
|
# sys.exit(1)
|
|
|
|
|
|
# 1) Find a feasible period and it's corresponding delays using the trimmed array.
|
|
self.load=max(loads)
|
|
self.slew=max(slews)
|
|
(feasible_delay_lh, feasible_delay_hl) = self.find_feasible_period()
|
|
debug.check(feasible_delay_lh>0,"Negative delay may not be possible")
|
|
debug.check(feasible_delay_hl>0,"Negative delay may not be possible")
|
|
|
|
# 2) Finds the minimum period without degrading the delays by X%
|
|
self.set_load_slew(max(loads),max(slews))
|
|
min_period = self.find_min_period(feasible_delay_lh, feasible_delay_hl)
|
|
debug.check(type(min_period)==float,"Couldn't find minimum period.")
|
|
debug.info(1, "Min Period: {0}n with a delay of {1} / {2}".format(min_period, feasible_delay_lh, feasible_delay_hl))
|
|
char_data["min_period"] = round_time(min_period)
|
|
|
|
# Make a list for each type of measurement to append results to
|
|
for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
|
|
"read1_power", "write0_power", "write1_power", "leakage_power"]:
|
|
char_data[m]=[]
|
|
|
|
# 3) Find the leakage power of the trimmmed and UNtrimmed arrays.
|
|
(full_array_leakage, trim_array_leakage)=self.run_power_simulation()
|
|
char_data["leakage_power"]=full_array_leakage
|
|
|
|
# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
|
|
for slew in slews:
|
|
for load in loads:
|
|
self.set_load_slew(load,slew)
|
|
# Find the delay, dynamic power, and leakage power of the trimmed array.
|
|
(success, delay_results) = self.run_delay_simulation()
|
|
debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(self.slew,self.load))
|
|
for k,v in delay_results.items():
|
|
if "power" in k:
|
|
# Subtract partial array leakage and add full array leakage for the power measures
|
|
char_data[k].append(v - trim_array_leakage + full_array_leakage)
|
|
else:
|
|
char_data[k].append(v)
|
|
|
|
|
|
|
|
return char_data
|
|
|
|
|
|
|
|
def add_data(self, data, port):
|
|
""" Add the array of data values """
|
|
debug.check(len(data)==self.word_size, "Invalid data word size.")
|
|
index = 0
|
|
for c in data:
|
|
if c=="0":
|
|
self.data_values[port][index].append(0)
|
|
elif c=="1":
|
|
self.data_values[port][index].append(1)
|
|
else:
|
|
debug.error("Non-binary data string",1)
|
|
index += 1
|
|
|
|
def add_address(self, address, port):
|
|
""" Add the array of address values """
|
|
debug.check(len(address)==self.addr_size, "Invalid address size.")
|
|
index = 0
|
|
for c in address:
|
|
if c=="0":
|
|
self.addr_values[port][index].append(0)
|
|
elif c=="1":
|
|
self.addr_values[port][index].append(1)
|
|
else:
|
|
debug.error("Non-binary address string",1)
|
|
index += 1
|
|
|
|
def add_noop(self, address, data, port):
|
|
""" Add the control values for a noop to a single port. """
|
|
#This is to be used as a helper function for the other add functions. Cycle and comments are omitted.
|
|
self.web_values[port].append(1)
|
|
self.csb_values[port].append(1)
|
|
|
|
self.add_data(data, port)
|
|
self.add_address(address, port)
|
|
|
|
def add_noop_all_ports(self, comment, address, data):
|
|
""" Add the control values for a noop to all ports. """
|
|
self.cycle_comments.append("Cycle {0:2d}\tPort All\t{1:5.2f}ns:\t{2}".format(len(self.cycle_times),
|
|
self.t_current,
|
|
comment))
|
|
self.cycle_times.append(self.t_current)
|
|
self.t_current += self.period
|
|
|
|
for readwrite_port in self.readwrite_ports:
|
|
self.add_noop(address, data, readwrite_port)
|
|
|
|
|
|
def add_read(self, comment, address, data, port):
|
|
""" Add the control values for a read cycle. """
|
|
self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
|
|
self.t_current,
|
|
comment,
|
|
port))
|
|
self.cycle_times.append(self.t_current)
|
|
self.t_current += self.period
|
|
|
|
self.web_values[port].append(1)
|
|
self.csb_values[port].append(0)
|
|
|
|
self.add_data(data, port)
|
|
self.add_address(address, port)
|
|
|
|
#Add noops to all other ports.
|
|
for readwrite_port in self.readwrite_ports:
|
|
if readwrite_port != port:
|
|
self.add_noop(address, data, readwrite_port)
|
|
|
|
def add_write(self, comment, address, data, port):
|
|
""" Add the control values for a write cycle. """
|
|
self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
|
|
self.t_current,
|
|
comment,
|
|
port))
|
|
self.cycle_times.append(self.t_current)
|
|
self.t_current += self.period
|
|
|
|
|
|
self.web_values[port].append(0)
|
|
self.csb_values[port].append(0)
|
|
|
|
self.add_data(data,port)
|
|
self.add_address(address,port)
|
|
|
|
#Add noops to all other ports.
|
|
for readwrite_port in self.readwrite_ports:
|
|
if readwrite_port != port:
|
|
self.add_noop(address, data, readwrite_port)
|
|
|
|
def create_test_cycles(self):
|
|
"""Returns a list of key time-points [ns] of the waveform (each rising edge)
|
|
of the cycles to do a timing evaluation. The last time is the end of the simulation
|
|
and does not need a rising edge."""
|
|
|
|
# Start at time 0
|
|
self.t_current = 0
|
|
|
|
# Cycle times (positive edge) with comment
|
|
self.cycle_comments = []
|
|
self.cycle_times = []
|
|
|
|
# Readwrite port Control logic signals each cycle
|
|
self.web_values = {readwrite_port:[] for readwrite_port in self.readwrite_ports}
|
|
self.csb_values = {readwrite_port:[] for readwrite_port in self.readwrite_ports}
|
|
|
|
# Address and data values for each address/data bit. A dict of 2d lists of size #ports x bits x cycles.
|
|
self.data_values={readwrite_port:[[] for i in range(self.word_size)] for readwrite_port in self.readwrite_ports}
|
|
#for i in range(self.word_size):
|
|
# self.data_values.append([])
|
|
self.addr_values={readwrite_port:[[] for i in range(self.addr_size)] for readwrite_port in self.readwrite_ports}
|
|
#for i in range(self.addr_size):
|
|
# self.addr_values.append([])
|
|
|
|
# Create the inverse address for a scratch address
|
|
inverse_address = ""
|
|
for c in self.probe_address:
|
|
if c=="0":
|
|
inverse_address += "1"
|
|
elif c=="1":
|
|
inverse_address += "0"
|
|
else:
|
|
debug.error("Non-binary address string",1)
|
|
|
|
# For now, ignore data patterns and write ones or zeros
|
|
data_ones = "1"*self.word_size
|
|
data_zeros = "0"*self.word_size
|
|
|
|
self.add_noop_all_ports("Idle cycle (no positive clock edge)",
|
|
inverse_address, data_zeros)
|
|
|
|
#Temporary logic. Loop through all ports with characterize logic.
|
|
for readwrite_port in self.readwrite_ports:
|
|
self.add_write("W data 1 address 0..00",
|
|
inverse_address,data_ones,readwrite_port)
|
|
|
|
self.add_write("W data 0 address 11..11 to write value",
|
|
self.probe_address,data_zeros,readwrite_port)
|
|
self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure
|
|
|
|
# This also ensures we will have a H->L transition on the next read
|
|
self.add_read("R data 1 address 00..00 to set DOUT caps",
|
|
inverse_address,data_zeros,readwrite_port)
|
|
|
|
self.add_read("R data 0 address 11..11 to check W0 worked",
|
|
self.probe_address,data_zeros,readwrite_port)
|
|
self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure
|
|
|
|
self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)",
|
|
inverse_address,data_zeros)
|
|
self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure
|
|
|
|
self.add_write("W data 1 address 11..11 to write value",
|
|
self.probe_address,data_ones,readwrite_port)
|
|
self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure
|
|
|
|
self.add_write("W data 0 address 00..00 to clear DIN caps",
|
|
inverse_address,data_zeros,readwrite_port)
|
|
|
|
# This also ensures we will have a L->H transition on the next read
|
|
self.add_read("R data 0 address 00..00 to clear DOUT caps",
|
|
inverse_address,data_zeros,readwrite_port)
|
|
|
|
self.add_read("R data 1 address 11..11 to check W1 worked",
|
|
self.probe_address,data_zeros,readwrite_port)
|
|
self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure
|
|
|
|
self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))",
|
|
self.probe_address,data_zeros)
|
|
|
|
|
|
|
|
def analytical_delay(self,sram, slews, loads):
|
|
""" Just return the analytical model results for the SRAM.
|
|
"""
|
|
delay_lh = []
|
|
delay_hl = []
|
|
slew_lh = []
|
|
slew_hl = []
|
|
for slew in slews:
|
|
for load in loads:
|
|
self.set_load_slew(load,slew)
|
|
bank_delay = sram.analytical_delay(self.slew,self.load)
|
|
# Convert from ps to ns
|
|
delay_lh.append(bank_delay.delay/1e3)
|
|
delay_hl.append(bank_delay.delay/1e3)
|
|
slew_lh.append(bank_delay.slew/1e3)
|
|
slew_hl.append(bank_delay.slew/1e3)
|
|
|
|
power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load)
|
|
#convert from nW to mW
|
|
power.dynamic /= 1e6
|
|
power.leakage /= 1e6
|
|
debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic))
|
|
debug.info(1,"Leakage Power: {0} mW".format(power.leakage))
|
|
|
|
data = {"min_period": 0,
|
|
"delay_lh": delay_lh,
|
|
"delay_hl": delay_hl,
|
|
"slew_lh": slew_lh,
|
|
"slew_hl": slew_hl,
|
|
"read0_power": power.dynamic,
|
|
"read1_power": power.dynamic,
|
|
"write0_power": power.dynamic,
|
|
"write1_power": power.dynamic,
|
|
"leakage_power": power.leakage
|
|
}
|
|
return data
|
|
|
|
def gen_data(self):
|
|
""" Generates the PWL data inputs for a simulation timing test. """
|
|
for readwrite_input in self.readwrite_ports:
|
|
for i in range(self.word_size):
|
|
sig_name="DIN_{0}[{1}] ".format(readwrite_input, i)
|
|
self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[readwrite_input][i], self.period, self.slew, 0.05)
|
|
# for write_port in range(OPTS.w_ports):
|
|
# for i in range(self.word_size):
|
|
# sig_name="DIN_WP{0}[{1}] ".format(write_port, i)
|
|
# self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[i], self.period, self.slew, 0.05)
|
|
|
|
def gen_addr(self):
|
|
"""
|
|
Generates the address inputs for a simulation timing test.
|
|
This alternates between all 1's and all 0's for the address.
|
|
"""
|
|
for readwrite_addr in self.readwrite_ports:
|
|
for i in range(self.addr_size):
|
|
sig_name = "A_{0}[{1}]".format(readwrite_addr,i)
|
|
self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[readwrite_addr][i], self.period, self.slew, 0.05)
|
|
# for write_addr in range(OPTS.w_ports):
|
|
# for i in range(self.addr_size):
|
|
# sig_name = "A_WP{0}[{1}]".format(write_addr,i)
|
|
# self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05)
|
|
# for read_addr in range(OPTS.r_ports):
|
|
# for i in range(self.addr_size):
|
|
# sig_name = "A_RP{0}[{1}]".format(read_addr,i)
|
|
# self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05)
|
|
|
|
|
|
def gen_control(self):
|
|
""" Generates the control signals """
|
|
#Multiport changes to control signals. This will most likely be changed at some point when control signals are better determined.
|
|
for readwrite_port in self.readwrite_ports:
|
|
self.stim.gen_pwl("CSB_{0}".format(readwrite_port), self.cycle_times, self.csb_values[readwrite_port], self.period, self.slew, 0.05)
|
|
self.stim.gen_pwl("WEB_{0}".format(readwrite_port), self.cycle_times, self.web_values[readwrite_port], self.period, self.slew, 0.05)
|
|
# for read_port in range(OPTS.r_ports):
|
|
# self.stim.gen_pwl("RPENB{0}".format(read_port), self.cycle_times, self.csb_values, self.period, self.slew, 0.05)
|
|
# for write_port in range(OPTS.w_ports):
|
|
# self.stim.gen_pwl("WPENB{0}".format(write_port), self.cycle_times, self.csb_values, self.period, self.slew, 0.05)
|
|
|
|
|
|
def gen_port_names(self):
|
|
"""Generates the port names to be used in characterization"""
|
|
self.readwrite_ports = []
|
|
self.write_ports = []
|
|
self.read_ports = []
|
|
for readwrite_port in range(OPTS.rw_ports):
|
|
self.readwrite_ports.append("RWP{0}".format(readwrite_port))
|
|
for write_port in range(OPTS.w_ports):
|
|
self.write_ports.append("WP{0}".format(write_port))
|
|
for read_port in range(OPTS.r_ports):
|
|
self.read_ports.append("RP{0}".format(read_port)) |