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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
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a00e1602748b458ee1c09da38d5428bf49a379ae
OpenRAM/compiler/verify
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Matt Guthaus 4a139b682d Add temporary options to LVS to allow name merging
2018-07-18 15:10:29 -07:00
..
__init__.py
Add DRC/LVS/PEX statistics in verbose=1 mode
2018-07-11 11:59:24 -07:00
assura.py
Add DRC/LVS/PEX statistics in verbose=1 mode
2018-07-11 11:59:24 -07:00
calibre.py
Add temporary options to LVS to allow name merging
2018-07-18 15:10:29 -07:00
magic.py
Standardize DRC and LVS message levels
2018-07-18 14:28:43 -07:00
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