mirror of https://github.com/VLSIDA/OpenRAM.git
572 lines
22 KiB
Python
572 lines
22 KiB
Python
from math import log
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import design
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from tech import drc, parameter
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import debug
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import contact
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from pinv import pinv
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from pbuf import pbuf
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from pand2 import pand2
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from pnand2 import pnand2
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from pinvbuf import pinvbuf
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from dff_inv import dff_inv
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from dff_inv_array import dff_inv_array
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import math
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from vector import vector
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from globals import OPTS
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class control_logic(design.design):
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"""
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Dynamically generated Control logic for the total SRAM circuit.
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"""
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def __init__(self, num_rows, words_per_row, port_type="rw"):
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""" Constructor """
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name = "control_logic_" + port_type
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(name))
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self.num_rows = num_rows
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self.words_per_row = words_per_row
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self.port_type = port_type
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if self.port_type == "rw":
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self.num_control_signals = 2
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else:
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self.num_control_signals = 1
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.setup_signal_busses()
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self.add_pins()
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self.add_modules()
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self.create_instances()
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def create_layout(self):
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""" Create layout and route between modules """
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self.place_instances()
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self.route_all()
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#self.add_lvs_correspondence_points()
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self.DRC_LVS()
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def add_pins(self):
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""" Add the pins to the control logic module. """
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for pin in self.input_list + ["clk"]:
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self.add_pin(pin,"INPUT")
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for pin in self.output_list:
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self.add_pin(pin,"OUTPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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def add_modules(self):
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""" Add all the required modules """
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dff = dff_inv()
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dff_height = dff.height
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self.ctrl_dff_array = dff_inv_array(rows=self.num_control_signals,columns=1)
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self.add_mod(self.ctrl_dff_array)
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self.and2 = pand2(height=dff_height)
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self.add_mod(self.and2)
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self.nand2 = pnand2(height=dff_height)
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self.add_mod(self.nand2)
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# Special gates: inverters for buffering
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# Size the clock for the number of rows (fanout)
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clock_driver_size = max(1,int(self.num_rows/4))
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self.clkbuf = pbuf(size=clock_driver_size, height=dff_height)
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self.add_mod(self.clkbuf)
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self.pbuf8 = pbuf(size=8, height=dff_height)
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self.add_mod(self.pbuf8)
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self.pbuf1 = pbuf(size=1, height=dff_height)
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self.add_mod(self.pbuf1)
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# self.inv = self.inv1 = pinv(size=1, height=dff_height)
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# self.add_mod(self.inv1)
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# self.inv2 = pinv(size=4, height=dff_height)
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# self.add_mod(self.inv2)
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# self.inv8 = pinv(size=16, height=dff_height)
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# self.add_mod(self.inv8)
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if (self.port_type == "rw") or (self.port_type == "r"):
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from importlib import reload
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c = reload(__import__(OPTS.replica_bitline))
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replica_bitline = getattr(c, OPTS.replica_bitline)
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delay_stages, delay_fanout = self.get_delay_chain_size()
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bitcell_loads = int(math.ceil(self.num_rows / 2.0))
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self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_"+self.port_type)
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self.add_mod(self.replica_bitline)
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def get_delay_chain_size(self):
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"""Determine the size of the delay chain used for the Sense Amp Enable """
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# FIXME: These should be tuned according to the additional size parameters
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delay_fanout = 3 # This can be anything >=2
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# Delay stages Must be non-inverting
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if self.words_per_row >= 8:
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delay_stages = 8
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elif self.words_per_row == 4:
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delay_stages = 6
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else:
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delay_stages = 4
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return (delay_stages, delay_fanout)
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def setup_signal_busses(self):
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""" Setup bus names, determine the size of the busses etc """
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# List of input control signals
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if self.port_type == "rw":
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self.input_list = ["csb", "web"]
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else:
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self.input_list = ["csb"]
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if self.port_type == "rw":
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self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
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else:
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self.dff_output_list = ["cs_bar", "cs"]
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "cs"]
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else:
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self.internal_bus_list = ["clk_buf", "gated_clk", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
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# Outputs to the bank
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if self.port_type == "r":
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self.output_list = ["s_en", "p_en"]
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elif self.port_type == "w":
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self.output_list = ["w_en"]
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else:
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self.output_list = ["s_en", "w_en", "p_en"]
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self.output_list.append("clk_buf")
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self.supply_list = ["vdd", "gnd"]
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def route_rails(self):
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""" Add the input signal inverted tracks """
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height = self.control_logic_center.y - self.m2_pitch
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offset = vector(self.ctrl_dff_array.width,0)
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self.rail_offsets = self.create_vertical_bus("metal2", self.m2_pitch, offset, self.internal_bus_list, height)
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def create_instances(self):
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""" Create all the instances """
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self.create_dffs()
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self.create_clk_rows()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_we_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_pen_row()
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self.create_sen_row()
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self.create_rbl()
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def place_instances(self):
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""" Place all the instances """
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# Keep track of all right-most instances to determine row boundary
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# and add the vdd/gnd pins
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self.row_end_inst = []
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# Add the control flops on the left of the bus
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self.place_dffs()
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row = 0
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# Add the logic on the right of the bus
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self.place_clkbuf_row(row=row)
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row += 1
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self.place_gated_clk_row(row=row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_we_row(row=row)
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height = self.w_en_inst.uy()
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control_center_y = self.w_en_inst.uy()
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_pen_row(row=row)
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self.place_sen_row(row=row+1)
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self.place_rbl(row=row+2)
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height = self.rbl_inst.uy()
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control_center_y = self.rbl_inst.by()
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# This offset is used for placement of the control logic in the SRAM level.
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self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y)
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# Extra pitch on top and right
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self.height = height + 2*self.m1_pitch
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# Max of modules or logic rows
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch
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else:
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self.width = max([inst.rx() for inst in self.row_end_inst]) + self.m2_pitch
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def route_all(self):
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""" Routing between modules """
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self.route_rails()
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self.route_dffs()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_rbl()
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self.route_sen()
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self.route_clk()
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self.route_supply()
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def create_rbl(self):
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""" Create the replica bitline """
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self.rbl_inst=self.add_inst(name="replica_bitline",
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mod=self.replica_bitline)
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self.connect_inst(["pre_p_en", "pre_s_en", "vdd", "gnd"])
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def place_rbl(self,row):
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""" Place the replica bitline """
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y_off = row * self.nand2.height + 2*self.m1_pitch
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# Add the RBL above the rows
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# Add to the right of the control rows and routing channel
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self.replica_bitline_offset = vector(0, y_off)
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self.rbl_inst.place(self.replica_bitline_offset)
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def create_clk_rows(self):
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""" Create the multistage and gated clock buffer """
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self.clkbuf_inst = self.add_inst(name="clkbuf",
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mod=self.clkbuf)
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self.connect_inst(["clk","clk_buf","vdd","gnd"])
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self.gated_clk_inst = self.add_inst(name="gated_clkbuf",
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mod=self.nand2)
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self.connect_inst(["cs","clk_buf","gated_clk","vdd","gnd"])
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def place_clkbuf_row(self,row):
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""" Place the multistage clock buffer below the control flops """
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x_off = self.ctrl_dff_array.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off,y_off)
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self.clkbuf_inst.place(offset)
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self.row_end_inst.append(self.clkbuf_inst)
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def place_gated_clk_row(self,row):
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""" Place the gated clk logic below the control flops """
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x_off = self.ctrl_dff_array.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off,y_off)
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self.gated_clk_inst.place(offset)
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self.row_end_inst.append(self.gated_clk_inst)
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def create_pen_row(self):
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# input: gated_clk, we_bar, output: pre_p_en
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self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
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mod=self.and2)
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self.connect_inst(["gated_clk", "we_bar", "pre_p_en", "vdd", "gnd"])
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# input: pre_p_en, output: p_en
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self.p_en_inst=self.add_inst(name="buf_p_en",
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mod=self.pbuf8)
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self.connect_inst(["pre_p_en", "p_en", "vdd", "gnd"])
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def place_pen_row(self,row):
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x_off = self.ctrl_dff_array.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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self.pre_p_en_offset = vector(x_off, y_off)
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self.pre_p_en_inst.place(offset=self.pre_p_en_offset,
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mirror=mirror)
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x_off += self.and2.width
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self.row_end_inst.append(self.pre_p_en_inst)
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def create_sen_row(self):
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""" Create the sense enable buffer. """
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# BUFFER FOR S_EN
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# input: pre_s_en, output: s_en
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self.s_en_inst=self.add_inst(name="buf_s_en",
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mod=self.pbuf8)
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self.connect_inst(["pre_s_en", "s_en", "vdd", "gnd"])
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def place_sen_row(self,row):
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"""
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The sense enable buffer gets placed to the far right of the
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row.
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"""
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x_off = self.ctrl_dff_array.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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self.s_en_offset = vector(x_off, y_off)
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self.s_en_inst.place(offset=self.s_en_offset,
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mirror=mirror)
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self.row_end_inst.append(self.s_en_inst)
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def route_dffs(self):
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""" Route the input inverters """
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if self.port_type == "r":
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control_inputs = ["cs"]
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else:
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control_inputs = ["cs", "we"]
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dff_out_map = zip(["dout_bar_{}".format(i) for i in range(2*self.num_control_signals - 1)], control_inputs)
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self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets)
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# Connect the clock rail to the other clock rail
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in_pos = self.ctrl_dff_inst.get_pin("clk").uc()
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mid_pos = in_pos + vector(0,2*self.m2_pitch)
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rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y)
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self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail_pos,
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rotate=90)
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self.copy_layout_pin(self.ctrl_dff_inst, "din_0", "csb")
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if (self.port_type == "rw"):
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self.copy_layout_pin(self.ctrl_dff_inst, "din_1", "web")
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def create_dffs(self):
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""" Add the three input DFFs (with inverters) """
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self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs",
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mod=self.ctrl_dff_array)
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self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list)
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def place_dffs(self):
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""" Place the input DFFs (with inverters) """
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self.ctrl_dff_inst.place(vector(0,0))
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def get_offset(self,row):
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""" Compute the y-offset and mirroring """
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y_off = row*self.nand2.height
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if row % 2:
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y_off += self.nand2.height
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mirror="MX"
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else:
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mirror="R0"
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return (y_off,mirror)
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def create_we_row(self):
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# input: we, gated_clk output: pre_w_en
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if self.port_type == "rw":
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self.pre_w_en_inst = self.add_inst(name="and_pre_w_en",
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mod=self.and2)
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self.connect_inst(["gated_clk", "we", "pre_w_en", "vdd", "gnd"])
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input_name = "pre_w_en"
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else:
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# No we signal is needed for write-only ports
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input_name = "gated_clk"
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# BUFFER FOR W_EN
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self.w_en_inst = self.add_inst(name="w_en_buf",
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mod=self.pbuf8)
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self.connect_inst([input_name, "w_en", "vdd", "gnd"])
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def place_we_row(self,row):
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x_off = self.ctrl_dff_inst.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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if self.port_type == "rw":
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pre_w_en_offset = vector(x_off, y_off)
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self.pre_w_en_inst.place(offset=pre_w_en_offset,
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mirror=mirror)
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x_off += self.nand2.width
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w_en_offset = vector(x_off, y_off)
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self.w_en_inst.place(offset=w_en_offset,
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mirror=mirror)
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self.row_end_inst.append(self.w_en_inst)
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def route_rbl(self):
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""" Connect the logic for the rbl_in generation """
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# Connect the NAND gate inputs to the bus
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pre_p_en_in_map = zip(["A", "B"], ["gated_clk", "we_bar"])
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self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets)
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# Connect the output of the precharge enable to the RBL input
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pre_p_en_out_pos = self.pre_p_en_inst.get_pin("Z").center()
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rbl_in_pos = self.rbl_inst.get_pin("en").center()
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mid1 = vector(rbl_in_pos.x,pre_p_en_out_pos.y)
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self.add_wire(("metal3","via2","metal2"),[pre_p_en_out_pos,mid1,rbl_in_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=pre_p_en_out_pos,
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rotate=90)
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=pre_p_en_out_pos,
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rotate=90)
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def connect_rail_from_right(self,inst, pin, rail):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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in_pos = inst.get_pin(pin).center()
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rail_pos = vector(self.rail_offsets[rail].x, in_pos.y)
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self.add_wire(("metal1","via1","metal2"),[in_pos, rail_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail_pos,
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rotate=90)
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def connect_rail_from_right_m2m3(self,inst, pin, rail):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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in_pos = inst.get_pin(pin).center()
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rail_pos = vector(self.rail_offsets[rail].x, in_pos.y)
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self.add_wire(("metal3","via2","metal2"),[in_pos, rail_pos])
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# Bring it up to M2 for M2/M3 routing
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=in_pos,
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rotate=90)
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=in_pos,
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rotate=90)
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=rail_pos,
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rotate=90)
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def connect_rail_from_left(self,inst, pin, rail):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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in_pos = inst.get_pin(pin).lc()
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rail_pos = vector(self.rail_offsets[rail].x, in_pos.y)
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self.add_wire(("metal1","via1","metal2"),[in_pos, rail_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=rail_pos,
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|
rotate=90)
|
|
|
|
def connect_rail_from_left_m2m3(self,inst, pin, rail):
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|
""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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|
in_pos = inst.get_pin(pin).lc()
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|
rail_pos = vector(self.rail_offsets[rail].x, in_pos.y)
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self.add_wire(("metal3","via2","metal2"),[in_pos, rail_pos])
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self.add_via_center(layers=("metal2","via2","metal3"),
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|
offset=in_pos,
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|
rotate=90)
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|
self.add_via_center(layers=("metal2","via2","metal3"),
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|
offset=rail_pos,
|
|
rotate=90)
|
|
|
|
|
|
def route_wen(self):
|
|
|
|
if self.port_type == "rw":
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|
wen_map = zip(["A", "B"], ["gated_clk", "we"])
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|
self.connect_vertical_bus(wen_map, self.pre_w_en_inst, self.rail_offsets)
|
|
|
|
self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()])
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|
else:
|
|
wen_map = zip(["A"], ["gated_clk"])
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|
self.connect_vertical_bus(wen_map, self.w_en_inst, self.rail_offsets)
|
|
|
|
self.connect_output(self.w_en_inst, "Z", "w_en")
|
|
|
|
def route_sen(self):
|
|
|
|
rbl_out_pos = self.rbl_inst.get_pin("out").bc()
|
|
in_pos = self.s_en_inst.get_pin("A").lc()
|
|
mid1 = vector(rbl_out_pos.x,in_pos.y)
|
|
self.add_wire(("metal1","via1","metal2"),[rbl_out_pos,mid1,in_pos])
|
|
|
|
self.connect_output(self.s_en_inst, "Z", "s_en")
|
|
|
|
def route_clk(self):
|
|
""" Route the clk and clk_buf_bar signal internally """
|
|
|
|
clk_pin = self.clkbuf_inst.get_pin("A")
|
|
self.add_layout_pin_segment_center(text="clk",
|
|
layer="metal2",
|
|
start=clk_pin.bc(),
|
|
end=clk_pin.bc().scale(1,0))
|
|
|
|
clkbuf_map = zip(["Z"], ["clk_buf"])
|
|
self.connect_vertical_bus(clkbuf_map, self.clkbuf_inst, self.rail_offsets, ("metal3", "via2", "metal2"))
|
|
|
|
clkbuf_map = zip(["Z"], ["gated_clk"])
|
|
self.connect_vertical_bus(clkbuf_map, self.gated_clk_inst, self.rail_offsets, ("metal3", "via2", "metal2"))
|
|
|
|
self.connect_output(self.clkbuf_inst, "Z", "clk_buf")
|
|
|
|
def connect_output(self, inst, pin_name, out_name):
|
|
""" Create an output pin on the right side from the pin of a given instance. """
|
|
|
|
out_pin = inst.get_pin(pin_name)
|
|
right_pos=out_pin.center() + vector(self.width-out_pin.cx(),0)
|
|
self.add_layout_pin_segment_center(text=out_name,
|
|
layer="metal1",
|
|
start=out_pin.center(),
|
|
end=right_pos)
|
|
|
|
|
|
|
|
def route_supply(self):
|
|
""" Add vdd and gnd to the instance cells """
|
|
|
|
max_row_x_loc = max([inst.rx() for inst in self.row_end_inst])
|
|
for inst in self.row_end_inst:
|
|
pins = inst.get_pins("vdd")
|
|
for pin in pins:
|
|
if pin.layer == "metal1":
|
|
row_loc = pin.rc()
|
|
pin_loc = vector(max_row_x_loc, pin.rc().y)
|
|
self.add_power_pin("vdd", pin_loc)
|
|
self.add_path("metal1", [row_loc, pin_loc])
|
|
|
|
pins = inst.get_pins("gnd")
|
|
for pin in pins:
|
|
if pin.layer == "metal1":
|
|
row_loc = pin.rc()
|
|
pin_loc = vector(max_row_x_loc, pin.rc().y)
|
|
self.add_power_pin("gnd", pin_loc)
|
|
self.add_path("metal1", [row_loc, pin_loc])
|
|
|
|
if (self.port_type == "rw") or (self.port_type == "r"):
|
|
self.copy_layout_pin(self.rbl_inst,"gnd")
|
|
self.copy_layout_pin(self.rbl_inst,"vdd")
|
|
|
|
self.copy_layout_pin(self.ctrl_dff_inst,"gnd")
|
|
self.copy_layout_pin(self.ctrl_dff_inst,"vdd")
|
|
|
|
|
|
|
|
def add_lvs_correspondence_points(self):
|
|
""" This adds some points for easier debugging if LVS goes wrong.
|
|
These should probably be turned off by default though, since extraction
|
|
will show these as ports in the extracted netlist.
|
|
"""
|
|
# pin=self.clk_inv1.get_pin("Z")
|
|
# self.add_label_pin(text="clk1_bar",
|
|
# layer="metal1",
|
|
# offset=pin.ll(),
|
|
# height=pin.height(),
|
|
# width=pin.width())
|
|
|
|
# pin=self.clk_inv2.get_pin("Z")
|
|
# self.add_label_pin(text="clk2",
|
|
# layer="metal1",
|
|
# offset=pin.ll(),
|
|
# height=pin.height(),
|
|
# width=pin.width())
|
|
|
|
pin=self.rbl_inst.get_pin("out")
|
|
self.add_label_pin(text="out",
|
|
layer=pin.layer,
|
|
offset=pin.ll(),
|
|
height=pin.height(),
|
|
width=pin.width())
|
|
|
|
|