mrg b9d993c88b Add dummy bitcell module. ... Modify bitcell logic to guess if bitcell is not "bitcell" No longer need to specify replica (and dummy) bitcell explicitly Add support for 1 or 2 port replica array.		2019-07-05 12:58:52 -07:00
..
sram.py	Merge branch 'pep8_cleanup' into dev	2019-06-14 08:47:10 -07:00
sram_1bank.py	Merge branch 'dev' into rbl_revamp	2019-07-03 14:05:28 -07:00
sram_2bank.py	Merge branch 'pep8_cleanup' into dev	2019-06-14 08:47:10 -07:00
sram_base.py	Add dummy bitcell module.	2019-07-05 12:58:52 -07:00
sram_config.py	Some cleanup	2019-07-05 08:18:58 -07:00